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? freescale semiconductor, inc., 2011. all rights reserved. freescale semiconductor data sheet: technical data this document provides an overview of the mpc8314e powerquicc? ii pro processo r features, including a block diagram showing the major functional components. the mpc8314e contains a core bui lt on power architecture? technology. it is a cost-effective, low-power, highly integrated host processor that addresses the requirements of several storage, consumer, and industrial applications, including main cpus and i/o pro cessors in network attached storage (nas), voice over ip (voip) router/gateway, intelligent wireless lan (wlan), set top boxes, industrial controllers, and wireless access points. the mpc8314e extends the powerquicc ii pr o family, adding higher cpu performance, new functionality, and faster interfaces while addressing the requirements relate d to time-to-market, price, power consumption, and package size. note that while the mpc8314e supports a security engine, the mpc8314 does not. document number: mpc8314eec rev. 2, 11/2011 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. mpc8314e features . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 7 4. power characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12 5. clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6. reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. ddr and ddr2 sdram . . . . . . . . . . . . . . . . . . . . . 16 8. duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9. ethernet: three-speed ethernet, mii management . 22 10. usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13. i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 14. pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 15. high-speed serial interfaces (hssi) . . . . . . . . . . . . 49 16. pci express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 17. timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 18. gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 19. ipic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 20. spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 21. tdm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 22. package and pin listings . . . . . . . . . . . . . . . . . . . . . 72 23. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 24. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 25. system design information . . . . . . . . . . . . . . . . . . . 95 26. ordering information . . . . . . . . . . . . . . . . . . . . . . . . 98 27. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mpc8314e powerquicc ii pro processor hardware specifications
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 2 freescale semiconductor overview 1 overview the mpc8314e incorporates the e300c3 (mpc603e-based) core, which includes 16 kbytes of l1 instruction and data caches, on-chip memory manage ment units (mmus), and floating-point support. in addition to the e300 core, the soc platform includes features such as dual enhanced three-speed 10, 100, 1000 mbps ethernet controllers (etsecs) with sgmii support, a 32- or 16-bit ddr1/ddr2 sdram memory controller, a security engine to accelerate control and data plane security protocols, and a high degree of software compatibility with previous-generation powerq uicc processor-based designs for backward compatibilit y and easier software migration. the mpc8314e also offers peripheral interfaces such as a 32-bit pci interface with up to 66 mhz operation, 16-bit enhanced local bus interface with up to 66 mhz operation, tdm inte rface, and usb 2.0 with an on-chip usb 2.0 phy. 8314e offers additional high-speed interconnect suppor t with dual single-lane pci express interfaces. when not used for pci express, the serdes inte rface may be configured to support sgmii. the mpc8314e security engine (sec 3.3) allows cpu-in tensive cryptographic opera tions to be offloaded from the main cpu core. this figure shows a block diagram of the mpc8314e. figure 1. mpc8314e block diagram 2 mpc8314e features the following features are supported in the mpc8314e. 2.1 e300 core the e300 core has the following features: ? operates at up to 400 mhz ? 16-kbyte instruction cache, 16-kbyte data cache etsec rtbi, sgmii duart interrupt i 2 c timers gpio enhanced ddr1/ddr2 controller controller pci i/o sequencer (ios) security note: the mpc8314 do not include a security engine. local bus, usb 2.0 hs host/device/otg ulpi on-chip hs phy spi engine 3.3 pci express x1 dma tdm rgmii, (r)mii etsec rtbi, sgmii rgmii, (r)mii 16-kb d-cache 16-kb i-cache e300c3 core with power management fpu pci express x1 mpc8314e
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 3 mpc8314e features ? one floating point unit and two integer units ? software-compatible with the freescale pr ocessor families implementing the powerpc architecture ? performance monitor 2.2 serial interfaces the following interfaces ar e supported in the mpc8314e. ? two enhanced tsecs (etsecs) ? two ethernet interfaces using one rg mii/mii/rmii/rtbi or sgmii (no gmii) ? dual uart, one i 2 c, and one spi interface 2.3 security engine the security engine is opt imized to handle all the al gorithms associated with ipsec, 802.11i, and iscsi. the security engine contai ns one crypto-channel, a controller, and a set of crypto execution units (eus). the execution units are: ? public key execution unit (pkeu) ? rsa and diffie-hellman (to 4096 bits) ? programmable field size up to 2048 bits ? elliptic curve cryptography (1023 bits) ? f2m and f(p) modes ? programmable field size up to 511 bits ? data encryption standard execution unit (deu) ? des, 3des ? two key (k1, k2) or three key (k1, k2, k3) ? ecb, cbc, cfb-64 and ofb-64 m odes for both des and 3des ? advanced encryption standard unit (aesu) ? implements the rinjdael symmetric key cipher ? key lengths of 128, 192, and 256 bits ? ecb, cbc, ccm, ctr, gcm, cmac, ofb, cfb, xcbc-mac and lrw modes ? xor acceleration ? message digest execution unit (mdeu) ? sha with 160-bit, 256-bit, 384- bit and 512-bit message digest ? sha-384/512 ? md5 with 128-bit message digest ? hmac with either algorithm ? random number generator (rng)
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 4 freescale semiconductor mpc8314e features ? combines a true random number generator (trng) and a nist-approved pseudo-random number generator (prng) (as described in annex c of fips140-2 and ansi x9.62). ? cyclical redundancy check hardware accelerator (crca) ? implements crc32c as required for iscsi header and payload checksums, crc32 as required for ieee 802 packets, as well as for programmable 32 bit crc polynomials 2.4 ddr memory controller the ddr1/ddr2 memory controller includes the following features: ? single 16- or 32-bit interface s upporting both ddr1 and ddr2 sdram ? support for up to 266 mhz data rate ? support for two physical banks (chip select s), each bank independently addressable ? 64-mbit to 2-gbit (for ddr1) a nd to 4-gbit (for ddr2) devices with x8/x16 data ports (no direct x4 support) ? support for one 16-bit device or two 8-bit devices on a 16-bit bus or two 16- bit devices on a 32-bit bus ? support for up to 16 simultaneous open pages ? supports auto refresh ? on-the-fly power management using cke ? 1.8-/2.5-v sstl2 compatible i/o 2.5 pci controller the pci controller includes the following features: ? designed to comply with pci local bus specification revision 2.3 ? single 32-bit data pci inte rface operates at up to 66 mhz ? pci 3.3-v compatible (not 5-v compatible) ? support for host and agent modes ? on-chip arbitration, supporting three external masters on pci ? selectable hardware-enforced coherency 2.6 tdm interface the tdm interface includes the following features: ? independent receive and transmit with de dicated data, clock and frame sync line ? separate or shared rck and tck whose sour ce can be either internal or external ? glueless interface to e1/t1 fram es and mvip, scas, and h.110 buses ? up to 128 time slots, where each slot ca n be programmed to be active or inactive ? 8- or 16-bit word widths ? the tdm transmitter sync signal (tfs), transm itter clock signal (tck ) and receiver clock
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 5 mpc8314e features ? signal (rck) can be configur ed as either input or output ? frame sync and data signals can be programmed to be sampled ei ther on the rising edge or on the falling edge of the clock ? frame sync can be programmed as active low or active high ? selectable delay (0?3 bits) between the frame sync signal and the beginning of the frame ? msb or lsb first support 2.7 usb dual-role controller the usb controller includes the following features: ? designed to comply with usb specification, rev. 2.0 ? supports operation as a stand-alone usb device ? supports one upstream facing port ? supports three program mable usb endpoints ? supports operation as a stand-alone usb host controller ? supports usb root hub with one downstream-facing port ? enhanced host controller interface (ehci) compatible ? supports high-speed (480 mbps), full-speed ( 12 mbps), and low-speed (1.5 mbps) operation. low-speed operation is supported only in host mode. ? supports utmi+ low pin interface (ulpi) or on-chip usb-2.0 full-speed/high-speed phy ? supports usb on-the-go mode, whic h includes both device and host f unctionality, when using an external ulpi phy 2.8 dual pci express interfaces the pci express interfaces have the following features: ? pci express 1.0a compatible ? x1 link width ? selectable operation as root complex or endpoint ? both 32- and 64-bit addressing ? 128-byte maximum payload size ? support for msi and intx interrupt messages ? virtual channel 0 only ? selectable traffic class ? full 64-bit decode with 32-bit wide windows ? dedicated descriptor based dma engine per in terface with separate read and write channels
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 6 freescale semiconductor mpc8314e features 2.9 dual enhanced three-speed et hernet controllers (etsecs) the etsecs include the following features: ? two sgmii/rgmii/mii/rmii/rtbi interfaces ? two controllers designed to comply with ieee std 802.3?, ieee 802.3u?, ieee 802.3x?, ieee 802.3z?, ieee 802.3au?, ieee 802.3ab?, and ieee std 1588? ? support for wake-on-magic packet?, a method to br ing the device from standby to full operating mode ? mii management interface for external phy control and status. 2.10 integrated programmable interrupt controller (ipic) the integrated programmable interrupt controller (ipic) provides a flexible solu tion for general-purpose interrupt control. the ipic program ming model is compatible with th e mpc8260 interrupt controller and supports external and internal discrete interrupt sources. interrupts can al so be redirected to an external interrupt controller. 2.11 power management controller (pmc) the mpc8314e supports a range of pow er management states that signi ficantly lower power consumption under the control of the power ma nagement controller. the pmc in cludes the following features: ? provides power management when the device is used in both pci host and agent modes ? pci power management 1.2 d0, d 1, d2, d3hot, and d3cold states ? pme generation in pci agent mode , pme detection in pci host mode ? wake-up from ethernet (magic packet), usb, gp io, and pci (pme input as host) while in the d1, d2 and d3hot states ? a new low-power standby power management state called d3warm ? the pmc, one ethernet port, and the gtm block remain pow ered via a split power supply controlled through an external power switch ? wake-up events include ethernet (magic pack et), gtm, gpio, or irq inputs and cause the device to transition back to normal operation ? pci agent mode is not be supported in d3warm state ? pci express-based pme events are not supported 2.12 serial peripheral interface (spi) the serial peripheral interface (spi ) allows the mpc8314e to exchange data between other powerquicc family chips, ethernet phys for configuration, and peripheral devices such as eeproms, real-time clocks, a/d converter s, and isdn devices. the spi is a full-duplex, synchronou s, character-oriented channel that supports a four-wire interface (receive, transmit, clock, and slave se lect). the spi block consists of tr ansmitter and receiver sections, an independent baud-rate generator, and a control unit.
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 7 electrical characteristics 2.13 dma controller, i 2 c, duart, enhanced local bus controller (elbc), and timers the integrated four-channel dma controller includes the following features: ? allows chaining (both extended and direct) th rough local memory-mapped chain descriptors (accessible by local masters) ? misaligned transfer capability for source/destination address ? supports external dreq , dack and done signals there is one i 2 c controller. this synchronous, multi-master buses can be c onnected to additional devices for expansion and system development. the duart supports full-duplex operation an d is compatible with the pc16450 and pc16550 programming models. 16-byte fifo s are supported for both the transmitter and the receiver. the elbc port allows connect ions with a wide variety of external dsps and asics. three separate state machines share the same external pins and can be programmed separately to a ccess different types of devices. the general-purpose chip select machine (gpcm) controls accesses to asynchronous devices using a simple handshake protocol . the three user programmable mach ines (upms) can be programmed to interface to synchronous devices or custom asic interfaces. each chip select can be conf igured so that the associated chip interface can be controlled by the gpcm or upm controller. both may exist in the same system. the local bus can operate at up to 66 mhz. the system timers include the foll owing features: periodic interrupt timer, real time clock, software watchdog timer, and two gene ral-purpose timer blocks. 3 electrical characteristics this section provides the ac and dc electrical sp ecifications and thermal characteristics for the mpc8314e, which is currently targeted to these sp ecifications. some of th ese specifications are independent of the i/o cell, but th ey are included for complete refere nce. these are not purely i/o buffer design specifications. 3.1 overall dc electrical characteristics this section covers the ratings, c onditions, and other characteristics. 3.1.1 absolute maximum ratings this table provides the absolute maximum ratings. table 1. absolute maximum ratings 1 characteristic symbol max value unit note core supply voltage vdd ?0.3 to 1.26 v ? pll supply voltage avdd ?0.3 to 1.26 v ? ddr1 dram i/o supply voltage gvdd ?0.3 to 2.7 v ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 8 freescale semiconductor electrical characteristics ddr2 dram i/o supply voltage gvdd ?0.3 to 1.9 v ? pci, local bus, duart, system control and power management, i 2 c, ethernet management, 1588 timer and jtag i/o voltage nvdd ?0.3 to 3.6 v 7 usb, and etsec i/o voltage lvdd ?0.3 to 2.75 or ?0.3 to 3.6 v6, 8 phy voltage usb phy usb_pll_pwr1 ?0.3 to 1.26 v ? usb_pll_pwr3, usb_vdda_bias, vdda ?0.3 to 3.6 v ? serdes phy xcorevdd, xpadvdd, sdavdd ?0.3 to 1.26 v ? input voltage ddr dram signals mv in ?0.3 to (gvdd + 0.3) v 2, 4 ddr dram reference mvref ?0.3 to (gvdd + 0.3) v 2, 4 etsec signals lv in ?0.3 to (lvdd + 0.3) v 3, 4 local bus, duart, sys_clk_in, system control and power management, i 2 c, and jtag signals nv in ?0.3 to (nvdd + 0.3) v 3, 4 pci nv in ?0.3 to (nvdd + 0.3) v 5 storage temperature range t stg ?55 to150 ?c? note: 1. functional and tested operating conditions are given in ta bl e 2 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresse s beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: mv in must not exceed gvdd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. caution: (n,l)v in must not exceed (n,l)vdd by more than 0.3 v. th is limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. (m,n,l)v in and mvref may overshoot/undershoot to a volt age and for a maximum duration as shown in figure 2 . 5. nv in on the pci interface may overshoot/undershoot according to the pci electrical specification for 3.3-v operation, as shown in figure 2 . 6. the max value of supply voltage shoul d be selected based on the rgmii mode. 7. nvdd means nvdd1_off, nvdd1_on, nvdd2_off, nvdd2_on, nvdd3_off, nvdd4_off 8. lvdd means lvdd1_off and lvdd2_on table 1. absolute maximum ratings 1 (continued) characteristic symbol max value unit note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 9 electrical characteristics 3.1.2 power supply voltage specification this table provides the recommended operating conditions for thempc8314e. note that the values in this table are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. table 2. recommended operating conditions characteristic symbol recommended value 1 unit status in d3 warm mode note serdes internal digital power xcorevdd 1.0 50 mv v switched off ? serdes internal digital power xcorevss 0.0 v ? ? serdes i/o digital power xpadvdd 1.0 50 mv v switched off ? serdes i/o digital power xpadvss 0.0 v ? ? serdes analog power for pll sdavdd 1.0 50 mv v switched off ? serdes analog power for pll sdavss 0.0 v ? ? dedicated 3.3 v analog power for usb pll usb_pll_pwr3 3.3 165mv v switched off ? dedicated 1.0 vanalog power for usb pll usb_pll_pwr1 1.0 50 mv v switched off ? dedicated analog ground for usb pll usb_pll_gnd 0.0 v ? ? dedicated usb power for usb bias circuit usb_vdda_bias 3.3 300 mv v switched off ? dedicated usb ground for usb bias circuit usb_vssa_bias 0.0 v ? ? dedicated power for usb transceiver usb_vdda 3.3 300 mv v switched off ? dedicated ground for usb transceiver usb_vssa 0.0 v ? ? core supply voltage vdd 1.0 50 mv v switched off ? core supply voltage vddc 1.0 50 mv v switched on ? analog power for e300 core apll avdd1 1.0 50 mv v switched off 6 analog power for system apll avdd2 1.0 50 mv v switched on 6 ddr and ddr2 dram i/o voltage gvdd 2.5 200 mv 1.8 100 mv v switched off ? differential reference voltage for ddr and ddr2 controller mvref gvdd /2 v switched off ? standard i/o voltage nvdd1_on 3.3 300 mv v switched on 1 standard i/o voltage nvdd2_on 3.3 300 mv v switched on 1 standard i/o voltage nvdd1_off 3.3 300 mv v switched off 2 standard i/o voltage nvdd2_off 3.3 300 mv v switched off 2 standard i/o voltage nvdd3_off 3.3 300 mv v switched off 2 standard i/o voltage nvdd4_off 3.3 300 mv v switched off 2 etsec/usbdr i/o supply lvdd1_off 2.5 125 mv 3.3 300 mv v switched off ? etsec i/o supply lvdd2_on 2.5 125 mv 3.3 300 mv v switched on ? analog and digital ground vss 0.0 v ? ? junction temperature range t a /t j 0 to105 ? c? 3
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 10 freescale semiconductor electrical characteristics this figure shows the undershoot and overshoot voltages at th e interfaces of the mpc8314e. figure 2. overshoot/undershoot voltage for gvdd/nvdd/lvdd 3.1.3 output driver characteristics this table provides information on the characteristics of the output driver strengths. the values are preliminary estimates. note: 1. the nvddx_on are static power suppl ies and can be connected together. 2. the nvddx_off are switchable power s upplies and can be connected together. 3. minimum temperature is specified with t a ;maximum temperature is specified with t j. 4. all power rails must be connected and power applied to the mpc8314 even if the ip interfaces are not used. 5. all i/o pins should be interfaced with peripherals operating at same voltage level. 6. this voltage is the input to the filter discussed in section 25.2, ?pll power supply filtering? and not necessarily the voltage at the avdd pin. 7. all 1v power supplies should be derived from the same source. table 3. output drive capability driver type output impedance ( ? ) supply voltag e local bus interface utilities signals 42 nvdd = 3.3 v pci signals 25 ddr signal 1 18 gvdd = 2.5 v ddr2 signal 1 18 gvdd = 1.8 v table 2. recommended operating conditions (continued) characteristic symbol recommended value 1 unit status in d3 warm mode note gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% g/l/nvdd + 20% g/l/nvdd g/l/nvdd + 5% of t interface 1 1. t interface refers to the clock period associated with the bus clock interface. v ih v il note:
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 11 electrical characteristics 3.2 power sequencing the mpc8314e does not require the core supply voltage (vdd and vddc) and i/o supply voltages (gvdd, lvddx_on, lvddx_off, nv ddx_on and nvddx_off) to be applied in any particular order. during the power ramp up, before the power s upplies are stable, if the i/o voltages are supplied before the core voltage, there may be a period of time when all input and output pins be actively driven and cause contention and/or excessive current. in or der to avoid actively driving the i/o pins and to eliminate excessive current draw, apply the continu ous core voltage (vddc) before the continuous i/o voltages (lvddx_on and nvddx_on) and switchable core voltage (v dd) before the switchable i/o voltages (gvdd, lvddx_off, and nvddx_off). porese t should be asserted before the continuous power supplies fully ramp up. in the case where the core voltage is app lied first, the core voltage supply must rise to 90% of its nominal value before the i/ o supplies reach 0.7 v, see figure 3 . once all the power supplies are stable, wait for a minimum of 32 clock cycles before negating poreset. the i/o power supply ramp-up slew ra te should be slower than 4v/100 ? s, this requirement is for esd circuit . this figure shows the power-up sequencing for switchable and continuous supplies. figure 3. power-up sequencing when switching from normal mode to d3 warm (standby) mode, first turn off th e switchable i/o voltage supply and then turn off the switchable core voltage supply. similarly, when switching from d3 warm (standby) mode to normal mode, first turn on the swit chable core voltage supply and then turn on the switchable i/o voltage supply. duart, system control, i 2 c, jtag,spi 42 nvdd = 3.3 v gpio signals 42 nvdd = 3.3 v etsec 42 lvdd = 3.3 v / 2.5 v 1 output impedance can also be adjusted th rough configurable options in ddr control driver register (ddrcdr). see the mpc8315e powerquicc ii pro integrated host processor family reference manual . table 3. output drive capability (continued) driver type output impedance ( ? ) supply voltag e continuous i/o voltage continuous core voltage 0.7 v 90% t v switchable i/o voltage switchable core voltage (vdd) 0.7 v 90% t v power sequence for continuous power supplies power sequence for switchable power supplies
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 12 freescale semiconductor power characteristics caution when the device is in d3 warm (standby) mode, all external voltage supplies applied to any i/o pins, with the exception of wake-up pins, must be turned off. applying supplied extern al voltage to any i/o pins, except the wake up pins, while the device is in d3 warm standby mode may cause permanent damage to the device. an example of the power-u p sequence is shown in figure 4 when implemented alo ng with low power d3 warm mode. figure 4. power up sequencing example with low power d3 warm mode 4 power characteristics this table shows the estimate d typical power dissipation fo r this family of devices. table 4. mpc8314e power dissipation (does not include i/o power dissipation) core frequency (mhz) csb frequency (mhz) typical 1,3 maximum 1,2 unit 266 133 1.116 1.646 w 333 133 1.142 1.665 w 400 133 1.167 1.690 w note: 1. the values do not include i/o supply power, but do include core, avdd, usb pll, and digital serdes power. 2. maximum power is based on a voltage of v dd = 1.05v, a junction temperature of t j = 105c, and an artificial smoker test. 3. typical power is based on a voltage of v dd = 1.05v, and an artificial smoker test running at room temperature. continuous i/o voltage continuous core voltage 90% poreset t sys_clk_in / t pci_sync_in >= 32 clock t v switchable core voltage switchable i/o voltage (lvddx_on, nvddx_on) (gvdd, lvddx_off, nvddx_off) vddc (vdd) 0
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 13 clock input timing this table shows the estimate d typical i/o power dissipation for this family of devices. 5 clock input timing this section provides the clock input dc and ac electrical characteristics for the mpc8314e. table 5. mpc8314e power dissipation interface frequency gv dd (1.8 v) gv dd (2.5 v) nv dd (3.3 v) lvdd1_off/ lvdd2_on (3.3v) lvdd2 _on (3.3v) vdd33pll, vdd33ana (3.3v) sata_vdd, vdd1io, vdd1ana (1.0v) xcorevdd, xpadvdd, sdavdd (1.0v) unit ddr 1 rs = 22 ? rt = 50 ? 266mhz, 32 bits ?0.323? ? ? ? ? ? w 200mhz, 32 bits ?0.291? ? ? ? ? ? w ddr 2 rs = 22 ? rt = 75 ? 266mhz, 32 bits 0.246 ? ? ? ? ? ? ? w 200mhz, 32bits 0.225 ? ? ? ? ? ? ? w pci i/o load = 50pf 33 mhz ? ? 0.120 ? ? ? ? ? w 66 mhz ? ? 0.249 ? ? ? ? ? w local bus i/o load = 20pf 66 mhz??? ? 0.056 ? ? ? w 50 mhz??? ? 0.040 ? ? ? w etsec i/o load = 20pf multiple by number of interface used mii, 25mhz ? ? ? 0.008 ? ? ? ? w rgmii, 125mhz (3.3v) ? ? ? 0.078 ? ? ? ? w rgmii, 125mhz (2.5v) ? ? ? 0.044 ? ? ? ? w usbdr controller (ulpi mode) load =20pf 60 mhz ? ? ? 0.078 ? ? ? ? w usbdr+ internal phy (utmi mode) 480 mhz ? ? ? 0.274 ? ? ? ? w pci express two x1lane 2.5 ghz ? ? ? ? ? ? ? 0.190 w other i/o ? ? ? 0.015 ? ? ? ? ? w
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 14 freescale semiconductor clock input timing 5.1 dc electrical characteristics this table provides the clock input (sys_clk_in/pci_sync_in) dc timing specifications for the mpc8314e. 5.2 ac electrical characteristics the primary clock source for the mpc8314e can be one of two inputs, sys_clk_in or pci_clk, depending on whether the device is configured in pci host or pci agent mode. this table provides the clock input (sys_clk_in/pci_clk) ac timing specifications for the mpc8314e. table 6. sys_clk_in dc electrical characteristics parameter condition symbol min max unit input high voltage ? v ih 2.4 nvdd + 0.3 v input low voltage ? v il -0.3 0.4 v sys_clk_in input current 0 v ? v in ?? nvdd i in ? 1 0 ? a sys_xtal_in input current 0 v ? v in ?? nvdd i in ? 4 0 ? a pci_sync_in input current 0 v ? v in ?? nvdd i in ? 1 0 ? a rtc_clk input current 0 v ? v in ?? nvdd i in ? 1 0 ? a usb_clk_in input current 0 v ? v in ? nvdd i in ? 1 0 ? a usb_xtal_in input current 0 v ? v in ?? nvdd i in ? 4 0 ? a table 7. sys_clk_in ac timing spec ifications parameter/condition symbol min typical max unit note sys_clk_in/pci_clk frequency f sys_clk_in 24 ? 66.67 mhz 1, 6, 7 sys_clk_in/pci_clk cycle time t sys_clk_in 15 ? 41.6 ns 6 sys_clk_in rise and fall time t kh , t kl 0.6 ? 4 ns 2, 6 pci_clk rise and fall time t pch , t pcl 0.6 0.8 1.2 ns 2 sys_clk_in/pci_clk duty cycle t khk /t sys_clk_in 40 ? 60 % 3, 6 sys_clk_in/pci_clk jitter ? ? ? 150 ps 4, 5, 6 note: 1. caution: the system, core, and security block must not exceed their respective maximum or minimum operating frequencies. 2. rise and fall times for sys_clk_in/pci_clk are specified at 20% to 80% of signal swing. 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter?short term and long term?and is guaranteed by design. 5. the sys_clk_in/pci_clk driver?s closed loop jitter bandwidth should be <500 kh z at ?20 db. the ban dwidth must be set low to allow cascade-connected pll- based devices to track sys_clk_in drivers with the sp ecified jitter. 6. the parameter names pci_clk and pci_sync_in are used interchangeably in this document. 7. spread spectrum is allowed up to 1% down-spread at 33khz.(max. rate).
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 15 reset initialization 6 reset initialization this section describes the dc and ac electrical specifications for the reset initialization timing and electrical requirements of the mpc8314e. 6.1 reset dc electrical characteristics this table provides the dc electrical characte ristics for the reset pins of the mpc8314e. 6.2 reset ac electrical characteristics this table provides the reset initialization ac timing specificati ons of the mpc8314e. table 8. reset pins dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih ? 2.0 nvdd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in 0 v ?? v in ?? nvdd ? 5 ? a output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v table 9. reset initializati on timing sp ecifications parameter/condition min max unit note required assertion time of hreset to activate reset flow 32 ? t pci_sync_in 1 required assertion time of poreset with stable clock applied to sys_clk_in when the device is in pci host mode 32 ? t sys_clk_in 2 required assertion time of poreset with stable clock applied to pci_sync_in when the device is in pci agent mode 32 ? t pci_sync_in 1 hreset assertion (output) 512 ? t pci_sync_in 1 input setup time for por configurat ion signals (cfg_reset_source[0:3] and cfg_sys_clkin_div ) with respect to negation of poreset when the device is in pci host mode 4?t sys_clk_in 2, 4 input setup time for por configurat ion signals (cfg_reset_source[0:3] and cfg_sys_clkin_div ) with respect to negation of poreset when the device is in pci agent mode 4?t pci_sync_in 1 input hold time for por configuration si gnals with respect to negation of hreset 0? ns ? time for the device to turn off por configuration signals with respect to the assertion of hreset ?4 ns 3 time for the device to turn on por config signals with respect to the negation of hreset 1?t pci_sync_in 1, 3
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 16 freescale semiconductor ddr and ddr2 sdram this table provides the pll lock times. 7 ddr and ddr2 sdram this section describes the dc and ac electrical specifications for the ddr sdram interface of the mpc8314e. note that ddr sdra m is gvdd(typ) = 2.5 v and ddr2 sdram is gvdd(typ) = 1.8 v. 7.1 ddr and ddr2 sdram dc electrical characteristics this table provides the recommended operating cond itions for the ddr2 sdram component(s) of the mpc8314e when gvdd(typ) = 1.8 v . note: 1. t pci_sync_in is the clock period of the input clock applied to pci_sync_in. when the device is in pci host mode the primary clock is applied to the sys_clk_in in put, and pci_sync_in period depends on the value of cfg_sys_clkin_div . 2. t sys_clk_in is the clock period of the input clock applied to sys_clk_in. it is only valid when t he device is in pci host mode. 3. por configuration signals consists of cfg_reset_source[0:3] and cfg_sys_clkin_div . 4. the parameter names cfg_sys_clkin_div and cfg_clkin_div are used interchangeably in this document. table 10. pll lock times parameter/condition min max unit note system pll lock times ? 100 ? s? e300 core pll lock times ? 100 ? s? serdes (sgmii/pci exp phy) pll lock times ? 100 ? s? usb phy pll lock times ? 100 ? s? table 11. ddr2 sdram dc electrical characteristics for gvdd(typ) = 1.8 v parameter/condition symbol min max unit note i/o supply voltage gvdd 1.7 1.9 v 1 i/o reference voltage mvref 0.49 ? gvdd 0.51 ? gvdd v 2 i/o termination voltage v tt mvref ? 0.04 mvref + 0.04 v 3 input high voltage v ih mvref+ 0.125 gvdd + 0.3 v ? input low voltage v il ?0.3 mvref ? 0.125 v ? output leakage current i oz ?9.9 9.9 ? a4 output high current (v out = 1.420 v, gvdd= 1.7v) i oh ?13.4 ? ma ? output low current (v out = 0.280 v) i ol 13.4 ? ma note: 1. gvdd is expected to be wit hin 50 mv of the dram gvdd at all times. 2. mvref is expected to be equal to 0.5 ? gvdd, and to track gvdd dc variations as measured at the receiver. peak-to-peak noise on mvref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mvref. this rail should track variations in the dc level of mvref. 4. output leakage is measured with all outputs disabled, 0 v ? v out ?? gvdd. table 9. reset initialization ti ming specifications (continued)
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 17 ddr and ddr2 sdram this table provides the ddr2 capacitance when gvdd(typ) = 1.8 v. this table provides the recommended operating co nditions for the ddr sdram component(s) of the mpc8314e when gvdd(typ) = 2.5 v . this table provides the ddr capacitance when gvdd(typ) = 2.5 v. this table provides the curren t draw characteristics for mv ref . table 12. ddr2 sdram capacitance for gvdd(typ) = 1.8 v parameter/condition symbol min max unit note input/output capacitance: dq, dqs c io 68p f1 delta input/output ca pacitance: dq, dqs c dio ?0 . 5p f1 note: 1. this parameter is sampled. gvdd = 1.8 v 0.090 v, f = 1 mhz, t a = 25c, v out = gvdd/2, v out (peak-to-peak) = 0.2 v. table 13. ddr sdram dc electrical characteristics for gvdd(typ) = 2.5 v parameter/condition symbol min max unit note i/o supply voltage gvdd 2.3 2.7 v 1 i/o reference voltage mvref 0.49 ? gvdd 0.51 ? gvdd v 2 i/o termination voltage v tt mvref ? 0.04 mvref + 0.04 v 3 input high voltage v ih mvref + 0.15 gvdd + 0.3 v ? input low voltage v il ?0.3 mvref ? 0.15 v ? output leakage current i oz ?9.9 ?9.9 ? a4 output high current (v out = 1.95 v, gvdd = 2.3v) i oh ?16.2 ? ma ? output low current (v out = 0.35 v) i ol 16.2 ? ma ? note: 1. gvdd is expected to be within 50 mv of the dram gvdd at all times. 2. mvref is expected to be equal to 0.5 ? gvdd, and to track gvdd dc variations as measured at the receiver. peak-to-peak noise on mvref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mvref. this rail should track variations in the dc level of mvref. 4. output leakage is measured with all outputs disabled, 0 v ? v out ?? gvdd. table 14. ddr sdram capacitance for gvdd(typ) = 2.5 v interface parameter/condition symbol min max unit note input/output capacitance: dq,dqs c io 68p f1 delta input/output ca pacitance: dq, dqs c dio ?0 . 5p f1 note: 1. this parameter is sampled. gvdd = 2.5 v 0.125 v, f = 1 mhz, t a =25 ? c, v out = gvdd/2, v out (peak-to-peak) = 0.2 v. table 15. current draw characteristics for mv ref parameter / condition symbol min max unit note current draw for mv ref i mvref ? 500 ? a1
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 18 freescale semiconductor ddr and ddr2 sdram 7.2 ddr and ddr2 sdram ac electrical characteristics this section provides the ac el ectrical characteristics for th e ddr and ddr2 sdram interface. 7.2.1 ddr and ddr2 sdram input ac timing specifications this table lists the input ac timing specific ations for the ddr2 sdram (gvdd(typ) = 1.8 v). this table lists the input ac timing specifications for the ddr sdram when gvdd(typ)=2.5 v. the following two tables list the input ac tim ing specifications for the ddr sdram interface. note: 1. the voltage regulator for mv ref must be able to supply up to 500 ? a current. table 16. ddr2 sdram input ac timing specifications for 1.8-v interface at recommended operating conditions with gvdd of 1.8v 100 mv parameter symbol min max unit note ac input low voltage v il ? mvref ? 0.45 v ? ac input high voltage v ih mvref + 0.45 ? v ? table 17. ddr sdram input ac timing specifications for 2.5 v interface at recommended operating conditions with gvdd of 2.5v 200 mv parameter symbol min max unit note ac input low voltage v il ? mvref ? 0.51 v ac input high voltage v ih mvref + 0.51 ? v table 18. ddr2 sdram input ac timing specifications at recommended operating conditions with gvdd of (1.8 v 100 mv) parameter symbol min max unit note controller skew for mdqs?mdq 266 mhz 200 mhz t ciskew ?875 ?1250 875 1250 ps 1, 2, 3 note: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any corresponding bit to be captured with mdqs[n]. this should be subtracted from the total timing budget. 2. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew .this can be determined by the following equat ion: tdiskew =+/?(t/4 ? abs(t ciskew )) where t is the clock period and abs(t ciskew ) is the absolute value of t ciskew . 3. memory controller odt value of 150 ? is recommended. table 19. ddr sdram input ac timing specifications at recommended operating conditions with gvdd of (2.5v 200 mv) parameter symbol min max unit note table 15. current draw characteristics for mv ref parameter / condition symbol min max unit note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 19 ddr and ddr2 sdram this figure shows the ddr sdra m input ac timing for the tolerated mdqs to mdq skew (t diskew ) figure 5. timing diagram for t diskew 7.2.2 ddr and ddr2 sdram outp ut ac timing specifications controller skew for mdqs?mdq 266 mhz 200 mhz t ciskew ?750 ?1250 750 1250 ps 1, 2 note: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any corresponding bit to be captured with mdqs[n]. this should be subtracted from the total timing budget. 2. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew . this can be determined by the following equation: t diskew =+/?(t/4 ? abs(t ciskew )) where t is the clock period and abs(t ciskew ) is the absolute value of t ciskew . table 20. ddr and ddr2 sdram ou tput ac timing specifications at recommended operating conditions parameter symbol 1 min max unit note mck[n] cycle time at mck[n]/mck [n] crossing t mck 7.5 10 ns 2 addr/cmd output setup with respect to mck 266 mhz 200 mhz t ddkhas 2.9 3.5 ? ? ns 3 addr/cmd output hold with respect to mck 266 mhz 200 mhz t ddkhax 3.15 4.20 ? ? ns 3 mcs [n] output setup with respect to mck 266 mhz 200 mhz t ddkhcs 3.15 4.20 ? ? ns 3 table 19. ddr sdram input ac timing specifications at recommended operating conditions with gvdd of (2.5v 200 mv) mck [n] mck[n] t mck mdq[x] mdqs[n] t diskew d1 d0 t diskew
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 20 freescale semiconductor ddr and ddr2 sdram mcs [n] output hold with respect to mck 266 mhz 200 mhz t ddkhcx 3.15 4.20 ? ? ns 3 mck to mdqs skew t ddkhmh ?0.6 0.6 ns 4 mdq//mdm output setup with respect to mdqs 266 mhz 200 mhz t ddkhds, t ddklds 900 1000 ? ? ps 5 mdq//mdm output hold with respect to mdqs 266 mhz 200 mhz t ddkhdx, t ddkldx 1100 1200 ? ? ps 5 mdqs preamble start t ddkhmp ?0.5 ? t mck ? 0.6 ?0.5 ? t mck + 0.6 ns 6 mdqs epilogue end t ddkhme ?0.6 0.6 ns 6 note: 1. the symbols used for timing specif ications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of t he reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes fr om the high (h) st ate until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq//mdm/mdqs. 4. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck[n] clock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqss override bits in the ti ming_cfg_2 register. this is typically set to the same delay as the clock adjust in the clk_cntl register. the timing parameters listed in th e table assume that these 2 parameters have been set to the same adjustment value. see the mpc8315e powerquicc ii pro integrated host processor family reference manual for a description and understanding of the timing modifications enabled by use of these bits. 5. determined by maximum possible skew between a data strobe (mdqs) and any corresponding bit of data (mdq), ecc (), or data mask (mdm). the data strobe should be centered in side of the data eye at the pins of the microprocessor. 6. all outputs are referenced to the rising edge of mck[ n] at the pins of the microprocessor. note that t ddkhmp follows the symbol conventions described in note 1. table 20. ddr and ddr2 sdram output ac timing specifi cations (continued) at recommended operating conditions parameter symbol 1 min max unit note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 21 ddr and ddr2 sdram this figure shows the ddr sd ram output timing for the mck to mdqs skew measurement (t ddkhmh ). figure 6. timing diagram for t ddkhmh this figure shows the ddr and dd r2 sdram output timing diagram. figure 7. ddr and ddr2 sdram output timing diagram mdqs mck mck t mck t ddkhmh(max) = 0.6 ns t ddkhmh(min) = ?0.6 ns mdqs addr/cmd t ddkhas , t ddkhcs t ddkhmh t ddklds t ddkhds mdq[x] mdqs[n] mck mck t mck t ddkldx t ddkhdx d1 d0 t ddkhax , t ddkhcx write a0 noop t ddkhme t ddkhmp
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 22 freescale semiconductor duart this figure provides the ac test load for the ddr bus. figure 8. ddr ac test load 8duart this section describes the dc and ac electrical specifications for the duart interface. 8.1 duart dc electrical characteristics this table lists the dc electrical ch aracteristics for the duart interface. 8.2 duart ac electrical specifications this table lists the ac timing parameters for the duart interface. 9 ethernet: three-speed ethernet, mii management this section provides the ac and dc electrical characteristics for three-speed, 10/100/1000, and mii management. table 21. duart dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2.1 nvdd + 0.3 v low-level input voltage nvdd v il ?0.3 0.8 v high-level output voltage, i oh = ?100 ? av oh nvdd ? 0.2 ? v low-level output voltage, i ol = 100 ? av ol ?0 . 2v input current (0 v ? v in ?? nvdd) i in ? 5 ? a table 22. duart ac timing specifications parameter value unit note minimum baud rate 256 baud ? maximum baud rate > 1,000,000 baud 1 oversample rate 16 ? 2 note: 1. actual attainable baud rate is limited by the latency of interrupt processing. 2. the middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. subsequent bit values are sampled each sixteenth sample. output z 0 = 50 ? gvdd/2 r l = 50 ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 23 ethernet: three-speed ethernet, mii management 9.1 etsec (10/100/1000 mbps)?mii/ rmii/rgmii/rtbi electrical characteristics the electrical characteristi cs specified here apply to all the medi a-independent interface (mii), reduced gigabit mii (rgmii), and re duced ten-bit interface (rtbi) signals except management data input/output (mdio) and management data clock (mdc). the mii and rmii is defined for 3.3 v, while the rgmii, and rtbi can operate at 2.5 v. the rgmii and rtbi follow the hewlett-p ackard reduced pin-count interface for gigabit ethernet physical layer device specification version 1.2a (9/22/2000). the electrical characteristics for mdio and mdc are specified in section 9.3, ?ethernet management interface electrical characteristics .? 9.1.1 mii, rmii, rgmii, and rtbi dc electrical characteristics all mii, rmii drivers and receivers comply with the dc parametric attributes specified in table 23 for 3.3-v operation and rgmii, rtbi dr ivers and receivers comply with the dc parametric attributes specified in table 24 . the rgmii and rtbi signals are base d on a 2.5 v cmos interface voltage as defined by jedec eia/jesd8?5. note etsec should be interfaced with peri pheral operating at same voltage level. table 23. mii/rmii (when operating at 3.3 v) dc electrical characteristics parameter symbol conditions min max unit supply voltage 3.3 v lvdd ??3 . 03 . 6v output high voltage v oh i oh = ?4.0 ma lvdd = min 2.40 lvdd + 0.3 v output low voltage v ol i ol = 4.0 ma lvdd = min v ss 0.50 v input high voltage v ih ??2 . 1l v d d + 0.3 v input low voltage v il ? ? ?0.3 0.90 v input high current i ih v in 1 = lvdd ? 40 ? a input low current i il v in 1 = vss ?600 ? ? a note: 1. the symbol v in , in this case, represents the lv in symbol referenced in ta b l e 1 and ta bl e 2 . table 24. rgmii/rtbi (when operating at 2.5 v) dc electrical characteristics parameters symbol conditions min max unit supply voltage 2.5 v lvdd ? ? 2.37 2.63 v output high voltage v oh i oh = ?1.0 ma lvdd = min 2.00 lvdd + 0.3 v output low voltage v ol i ol = 1.0 ma lvdd = min v ss ? ? 0.3 0.40 v input high voltage v ih ? lvdd = min 1.7 lvdd + 0.3 v input low voltage v il ? lvdd =min ?0.3 0.70 v input high current i ih v in 1 = lvdd ? 15 ? a input low current i il v in 1 = vss ?15 ? ? a
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 24 freescale semiconductor ethernet: three-speed ethernet, mii management 9.2 mii, rmii, rgmii, and rtbi ac timing specifications the ac timing specifications for mii, rmii, rgmii, and rtbi ar e presented in this section. 9.2.1 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. 9.2.1.1 mii transmit ac timing specifications this table provides the mii transmit ac timing sp ecifications. this figure shows the mii transmit ac timing diagram. figure 9. mii transmit ac timing diagram note: 1. the symbol v in , in this case, represents the lv in symbol referenced in ta b l e 1 and ta bl e 2 . table 25. mii transmit ac timing specifications at recommended operating conditions with lvdd of 3.3 v 300 mv. parameter/condition symbol 1 min typ max unit tx_clk clock period 10 mbps t mtx ?400?ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh/ t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1 5 15 ns tx_clk data clock rise v il (min) to v ih (max) t mtxr 1.0 ? 4.0 ns tx_clk data clock fall v ih (max) to v il (min) t mtxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outp uts (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to th ree letters representing the cloc k of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall ti mes, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 24. rgmii/rtbi (when operating at 2.5 v) dc electrical characteristics (continued) parameters symbol conditions min max unit tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 25 ethernet: three-speed ethernet, mii management 9.2.1.2 mii receive ac timing specifications this table provides the mii rece ive ac timing specifications. this figure provides the ac test load for etsec. figure 10. etsec ac test load this figure shows the mii receive ac timing diagram. figure 11. mii receive ac timing diagram rmii ac timing specifications table 26. mii receive ac timing specifications at recommended operating conditions with lvdd of 3.3 v 300 mv parameter/condition symbol 1 min typ max unit rx_clk clock period 10 mbps t mrx ?400?ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns rx_clk clock rise v il (min) to v ih (max) t mrxr 1.0 ? 4.0 ns rx_clk clock fall time v ih (max) to v il (min) t mrxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representat ion is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. the frequency of rx_clk should not exceed the tx_clk by more than 300 ppm output z 0 = 50 ? lvdd/2 r l = 50 ? rx_clk rxd[3:0] t mrdxkh t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 26 freescale semiconductor ethernet: three-speed ethernet, mii management 9.2.2 rmii ac timing specifications this section describes the rmii transm it and receive ac timing specifications. 9.2.2.1 rmii transmit ac timing specifications this section describes the rmii tr ansmit and receive ac timing speci fications. this table provides the rmii transmit ac timing specifications. this figure shows the rmii transmit ac timing diagram. figure 12. rmii transmit ac timing diagram 9.2.2.2 rmii receive ac timing specifications this table provides the rmii r eceive ac timing specifications. table 27. rmii transmit ac timing specifications at recommended operating conditions with lvdd of 3.3 v 300 mv parameter/condition symbol 1 min typ max unit ref_clk clock t rmx ?20?ns ref_clk duty cycle t rmxh/ t rmx 35 ? 65 % ref_clk to rmii data txd[1:0], tx_en delay t rmtkhdx 2 ? 10 ns ref_clk data clock rise v il (min) to v ih (max) t rmxr 1.0 ? 4.0 ns ref_clk data clock fall v ih (max) to v il (min) t rmxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specificat ions herein follow the pattern of t (first three letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t rmtkhdx symbolizes rmii transmit timing (rmt) for the time t rmx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t rmx represents the rmii(rm) reference (x) cloc k. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 28. rmii receive ac timing specifications at recommended operating conditions with lvdd of 3.3 v 300 mv parameter/condition symbol 1 min typ max unit ref_clk clock period t rmx ?20?ns ref_clk duty cycle t rmxh /t rmx 35 ? 65 % ref_clk txd[1:0] t rmtkhdx t rmx t rmxh t rmxr t rmxf tx_en
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 27 ethernet: three-speed ethernet, mii management this figure provides the ac test load. figure 13. ac test load this figure shows the rmii receive ac timing diagram. figure 14. rmii receive ac timing diagram 9.2.3 rgmii and rtbi ac timing specifications this table presents the rgmii a nd rtbi ac timing specifications. rxd[1:0], crs_dv, rx_er setup time to ref_clk t rmrdvkh 4.0 ? ? ns rxd[1:0], crs_dv, rx_er hold time to ref_clk t rmrdxkh 2.0 ? ? ns ref_clk clock rise v il (min) to v ih (max) t rmxr 1.0 ? 4.0 ns ref_clk clock fall time v ih (max) to v il (min) t rmxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first three letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t rmrdvkh symbolizes rmii receive timing (rmr) with respect to the time data input signals (d) reach the valid state (v) relative to the t rmx clock reference (k) going to the high (h) state or setup time. also, t rmrdxkl symbolizes rmii receive timing (rmr) with respect to the time data input signals (d) went invalid (x) relative to the t rmx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representati on is based on three letters repr esenting the clock of a particul ar functional. for example, the subscript of t rmx represents the rmii (rm) reference (x) cloc k. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 29. rgmii and rtbi ac timing specifications at recommended operating conditions (see table 2 ) parameter/condition symbol 1 min typ max unit data to clock output skew (at transmitter) t skrgt ?0.6 ? 0.6 ns data to clock input skew (at receiver) 2 t skrgt 1.0 ? 2.6 ns table 28. rmii receive ac timing specifications (continued) at recommended operating conditions with lvdd of 3.3 v 300 mv parameter/condition symbol 1 min typ max unit output z 0 = 50 ? nvdd / 2 r l = 50 ? ref_clk rxd[1:0] t rmrdxkh t rmx t rmxh t rmxr t rmxf crs_dv rx_er t rmrdvkh valid data
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 28 freescale semiconductor ethernet: three-speed ethernet, mii management clock cycle duration 3 t rgt 7.2 8.0 8.8 ns duty cycle for 1000base-t 4, 5 t rgth /t rgt 45 50 55 % duty cycle for 10base-t and 100base-tx 3, 5 t rgth /t rgt 40 50 60 % rise time (20%?80%) t rgtr ? ? 0.75 ns fall time (20%?80%) t rgtf ? ? 0.75 ns gtx_clk125 reference clock period t g12 6 ?8 . 0?n s gtx_clk125 reference clock duty cycle t g125h /t g125 47 ? 53 % note: 1. note that, in general, the clock reference symbol representation for this section is based on the symbols rgt to represent rg mii and rtbi timing. for example, the subscript of t rgt represents the rtbi (t) receive (rx) cloc k. note also that the notation for rise (r) and fall (f) times follows the clock symbol that is being represented. for symbols representing skews, the subscript is ske w (sk) followed by the clock that is being skewed (rgt). 2. this implies that pc board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is add ed to the associated clock signal. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long a s the minimum duty cycle is not violated and stretching occu rs for no more than three t rgt of the lowest speed transitioned between. 5. duty cycle reference is lvdd/2. 6. this symbol is used to represent the external gtx_clk125 an d does not follow the original symbol naming convention. gtx_clk supply voltage is fixed at 3.3v inside the chip. if phy supplie s a 2.5 v clock signal on this input, set tscomobi bit of system i/o configuration register (sicrh) as 1. see the mpc8315e powerquicc ii pro integrated ho st processor family reference manual . 7. the frequency of rx_clk should not exceed the tx_clk by more than 300 ppm table 29. rgmii and rtbi ac timi ng specifications (continued) at recommended operating conditions (see table 2 ) parameter/condition symbol 1 min typ max unit
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 29 ethernet: three-speed ethernet, mii management this figure shows the rgmii and rtbi ac timing and multiplexing diagrams. figure 15. rgmii and rtbi ac timing and multiplexing diagrams 9.3 ethernet management interface electrical characteristics the electrical characteristics speci fied here apply to mii management interface signals management data input/output (mdio) and management data clock (mdc). the electrical characteristics for mii, rmii, rgmii, and rtbi are specified in section 9.1, ?etsec (10/100/1000 mbps)?mii/rmii/rgmii/rtbi electrical characteristics .? 9.3.1 mii management dc electrical characteristics the mdc and mdio are defined to ope rate at a supply voltage of 3.3 v. the dc electrical characteristics for mdio and mdc are provided in this table. table 30. mii management dc electrical characteristics powered at 3.3 v parameter symbol conditions min max unit supply voltage (3.3 v) nvdd ? ? 3.0 3.6 v output high voltage v oh i oh = ?1.0 ma nvdd = min 2.10 nvdd + 0.3 v output low voltage v ol i ol = 1.0 ma nvdd = min v ss 0.50 v input high voltage v ih ??2 . 0 0?v input low voltage v il ? ? ? 0.80 v input high current i ih nvdd = max v in 1 = 2.1 v ? 40 ? a gtx_clk t rgt t rgth t skrgt tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rxd[8:5][3:0] rxd[7:4][3:0] rx_clk (at controller) t skrgt t skrgt t skrgt
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 30 freescale semiconductor ethernet: three-speed ethernet, mii management 9.3.2 mii management ac electrical specifications this table provides the mii mana gement ac timing specifications. input low current i il nvdd = max v in = 0.5 v ?600 ? ? a note: 1. the symbol v in , in this case, represents the nv in symbol referenced in ta bl e 1 and ta b l e 2 . table 31. mii management ac timing specifications at recommended operating conditions with nvdd is 3.3 v 300 mv parameter/condition symbol 1 min typ max unit note mdc frequency f mdc ?2.5?mhz2 mdc period t mdc ? 400 ? ns ? mdc clock pulse width high t mdch 32 ? ? ns ? mdc to mdio delay t mdkhdx 10 ? 170 ns 3 mdio to mdc setup time t mddvkh 5??ns? mdio to mdc hold time t mddxkh 0??ns? mdc rise time t mdcr ? ? 10 ns ? mdc fall time t mdhf ? ? 10 ns ? note: 1. the symbols used for timing specificat ions herein follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropri ate letter: r (rise) or f (fall). 2. this parameter is dependent on the csb_c lk speed (that is, for a csb_clk of 133 mhz, the maximum frequency is 4.16 mhz and the minimum frequency is 0.593 mhz). 3. this parameter is dependent on the csb_clk speed (that is, for a csb_clk of 133 mhz, the delay is 60 ns). table 30. mii management dc electrical characteristics powered at 3.3 v (continued) parameter symbol conditions min max unit
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 31 ethernet: three-speed ethernet, mii management this figure shows the mii ma nagement ac timing diagram. figure 16. mii management interface timing diagram 9.4 1588 timer specifications this section describes the dc and ac elec trical specifications for the 1588 timer. 9.4.1 1588 timer dc specifications this table provides the 1588 timer dc specifications. 9.4.2 1588 timer ac specifications this table provides the 1588 timer ac specifications. table 32. gpio dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ? 2.0 nvdd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in 0 v ?? v in ?? nvdd ? 5 ? a table 33. 1588 timer ac specifications parameter symbol min max unit note timer clock cycle time t tmrck 070mhz1 input setup to timer clock t tmrcks ???2, 3 input hold from timer clock t tmrckh ???2, 3 output clock to output valid t gclknv 06ns timer alarm to output valid t tmral ??? 2 mdc t mddxkh t mdc t mdch t mdcr t mdcf t mddvkh t mdkhdx mdio mdio (input) (output)
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 32 freescale semiconductor ethernet: three-speed ethernet, mii management 9.5 sgmii interface electrical characteristics each sgmii port features a 4-wi re ac-coupled serial link from th e dedicated serdes interface of mpc8315e as shown in figure 17 , where c tx is the external (on board) ac-coupled capacitor. each output pin of the serdes transmit ter differential pair features 50- ?? output impedance. each input of the serdes receiver differential pair features 50- ? on-die termination to xcor evss. the reference circuit of the serdes transmitter and receiver is shown in figure 48 . when an etsec port is configured to operate in sg mii mode, the parallel inte rface?s output signals of this etsec port can be left floa ting. the input signals should be te rminated based on the guidelines described in section 25.4, ?connection recommendations,? as long as such ter mination does not violate the desired por configuration require ment on these pins, if applicable. when operating in sgmii mode, the tsec_gtx_clk125 clock is not required for this port. instead, serdes reference clock is required on sd_ref_clk and sd_ref_clk pins. 9.5.1 dc requirements for sgmi i sd_ref_clk and sd_ref_clk the characteristics and dc requir ements of the separate serdes reference clock are described in section 15, ?high-speed serial interfaces (hssi).? 9.5.2 ac requirements for sgmii sd_ref_clk and sd_ref_clk this table lists the sgmii serdes reference clock ac requirements. please not e that sd_ref_clk and sd_ref_clk are not intended to be used with, and should not be clocked by, a spread spectrum clock source. 9.5.3 sgmii transmitter and receiver dc electrical characteristics table 35 and table 36 describe the sgmii serdes transmitter and receiver ac-coupled dc electrical characteristics. transmi tter dc characteristics ar e measured at the transmitter outputs (sd_tx[n] and sd_tx [n]) as depicted in figure 16 . note: 1. the timer can operate on rtc_clock or tmr_clock. these clocks get muxed and any one of them can be selected. 2. asynchronous signals. 3. inputs need to be stable at least one tmr clock. table 34. sd_ref_clk and sd_ref_clk ac requirements symbol parameter description min typical max unit note t ref refclk cycle time ? 8 ? ns ? t refcj refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles ??100ps? t refpj phase jitter. deviation in edge location with respect to mean edge location ?50 ? 50 ps ? table 33. 1588 timer ac specifications (continued) parameter symbol min max unit note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 33 ethernet: three-speed ethernet, mii management table 35. sgmii dc transmitter electrical characteristics parameter symbol min typ max unit note supply voltage xcorevdd 0.95 1.0 1.05 v ? output high voltage voh ? ? xcorevdd -typ /2 + |v od | -max /2 mv 1 output low voltage vol xcorevdd -typ /2 - |v od | -max /2 ??mv1 output ringing v ring ??1 0%? output differential voltage 2, 3, 5 |v od | 323 500 725 mv equalization setting: 1.0x 296 459 665 equalization setting: 1.09x 269 417 604 equalization setting: 1.2x 243 376 545 equalization setting: 1.33x 215 333 483 equalization setting: 1.5x 189 292 424 equalization setting: 1.71x 162 250 362 equalization setting: 2.0x output offset voltage v os 425 500 575 mv 1, 4 output impedance (single-ended) r o 40 ? 60 ? ? mismatch in a pair r o ??1 0%? change in v od between ?0? and ?1? |v od |? ? 2 5m v? change in v os between ?0? and ?1? v os ??2 5m v? output current on short to gnd i sa , i sb ??4 0m a? note: 1. this will not align to dc-coupled sgmii. xcorevdd -typ =1.0v. 2. |v od | = |v txn - v tx n |. |v od | is also referred as output differential peak voltage. v tx-diffp-p = 2*|v od | . 3. the |v od | value shown in the table assumes the following transmit equalization setting in the txeqa (for serdes lane a) or txeqe (for serdes lane e) bit field of mpc8315e?s serdes control register 0: ? the lsbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in table. 4. v os is also referred to as output common mode voltage. 5. the |v od | value shown in the typ column is based on the condition of xcorevdd -typ =1.0v, no common mode offset variation (v os = 500 mv), serdes transmitter is terminated with 100- ? differential load between tx[n] and tx [n]. ? ? ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 34 freescale semiconductor ethernet: three-speed ethernet, mii management figure 17. 4-wire ac-coupled sgmii serial link connection example figure 18. sgmii transmitter dc measurement circuit table 36. sgmii dc receiver electrical characteristics parameter symbol min typ max unit note supply voltage xcorevdd 0.95 1.0 1.05 v ? dc input voltage range ? n/a ? 1 input differential voltage eq = 0 v rx_diffp-p 100 ? 1200 mv 2, 4 eq = 1 175 ? loss of signal threshold eq = 0 vlos 30 ? 100 mv 3, 4 eq = 1 65 ? 175 mpc8315e sgmii serdes interface 50 ? 50 ? transmitter txn rxm tx n rx m receiver c tx c tx 50 ? 50 ? rxn rx n receiver transmitter txm tx m c tx c tx 50 ? 50 ? 50 ? 50 ? 50 ? transmitter txn tx n 50 ? v os v od mpc8315e sgmii serdes interface 50 ? 50 ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 35 ethernet: three-speed ethernet, mii management 9.5.4 sgmii ac timing specifications this section describes the sgmii transmit and recei ve ac timing specifications . transmitter and receiver characteristics are meas ured at the transmitte r outputs (tx[n] and tx [n]) or at the r eceiver inputs (rx[n] and rx [n]) as depicted in figure 20 respectively. 9.5.4.1 sgmii transmit ac timing specifications this table provides the sgmii tran smit ac timing targets. a source synchronous clock is not provided. 9.5.4.2 sgmii receive ac timing specifications this table provides the sgmii r eceive ac timing specifications. source synchronous clocking is not supported. clock is recovered from the data. figure 19 shows the sgmii receiv er input compliance mask eye diagram. input ac common mode voltage v cm_acp-p ? ? 100 mv 5 receiver differential input impedance z rx_diff 80 100 120 ? ? receiver common mode input impedance z rx_cm 20 ? 35 ? ? common mode input voltage v cm ?v xcorevss ?v6 note: 1. input must be externally ac-coupled. 2. v rx_diffp-p is also referred to as peak to peak input differential voltage 3. the concept of this parameter is equivalent to the electrical idle detect threshold parameter in pci express. refer to pci express differential receiver (rx) input spec ifications section for further explanation. 4. the eq shown in the table refers to the rxeqa or rxeqe bit field of mpc8315e?s serdes control register 0. 5. v cm_acp-p is also referred to as peak to peak ac common mode voltage. 6. on-chip termination to xcorevss. table 37. sgmii transmit ac timing specifications at recommended operating conditions with xcorevdd = 1.0v 5%. parameter symbol min typ max unit note deterministic jitter jd ? ? 0.17 ui p-p ? total jitter jt ? ? 0.35 ui p-p ? unit interval ui 799.92 800 800.08 ps ? v od fall time (80%-20%) tfall 50 ? 120 ps ? v od rise time (20%-80%) t rise 50 ? 120 ps ? note: 1. each ui is 800 ps 100 ppm. table 36. sgmii dc receiver electrical characteristics (continued) parameter symbol min typ max unit note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 36 freescale semiconductor ethernet: three-speed ethernet, mii management figure 19. sgmii receiver input compliance mask table 38. sgmii receive ac timing specifications at recommended operating conditions with xcorevdd = 1.0v 5%. parameter symbol min typ max unit note deterministic jitter tolerance jd 0.37 ? ? ui p-p 1 combined deterministic and random jitter tolerance jdr 0.55 ? ? ui p-p 1 sinusoidal jitter tolerance jsin 0.1 ? ? ui p-p 1 total jitter tolerance jt 0.65 ? ? ui p-p 1 bit error ratio ber ? ? 10 -12 ? unit interval ui 799.92 800 800.08 ps 2 ac coupling capacitor c tx 5?200nf3 note: 1. measured at receiver. 2. each ui is 800 ps 100 ppm. 3. the external ac coupling capacitor is required. it?s recommended to be placed near the device transmitter outputs. 4. refer to rapidio tm 1x/4x lp serial physical layer specificatio n for interpretation of jitter specifications. time (ui) receiver differential input voltage 0 0.275 0.4 0.6 0.725 ? v rx_diffp-p-min /2 v rx_diffp-p-min /2 ? v rx_diffp-p-max /2 v rx_diffp-p-max /2 0 1
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 37 usb figure 20. sgmii ac test/measurement load 10 usb 10.1 usb dual-role controllers this section provides the ac and dc electrica l specifications for the usb-ulpi interface. 10.1.1 usb dc electrical characteristics this table lists the dc electrical ch aracteristics for the usb interface. 10.1.2 usb ac electrical specifications this table lists the general timing parameters of the usb-ulpi interface. table 39. usb dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2 lvdd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current i in ? 5 ? a high-level output voltage, i oh = ?100 ? av oh lvdd ? 0.2 ? v low-level output voltage, i ol = 100 ? av ol ?0 . 2v note: 1. the symbol v in , in this case, represents the nv in symbol referenced in ta bl e 1 and ta b l e 2 . table 40. usb general timing parameters parameter symbol 1 min max unit note usb clock cycle time t usck 15 ? ns 1, 2 input setup to usb clock?all inputs t usivkh 4?n s1 , 4 input hold to usb clock?all inputs t usixkh 1?n s1 , 4
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 38 freescale semiconductor usb figure 21 and figure 22 provide the ac test load and signals for the usb, respectively. figure 21. usb ac test load figure 22. usb signals 10.2 on-chip usb phy this section provides the ac and dc electrical specifications for the usb phy interface of the mpc8314e. for details refer to tables 7-7 through 7-10, and table 7-14 in the usb 2.0 specifications document , and the pull-up/down resistors ecn update s, all available at www.usb.org. this table provides the usb clock input (usb_clk_in) dc ti ming specifications. usb clock to output valid?all outputs t uskhov ?9n s1 output hold from usb clock?all outputs t uskhox 1?n s1 note: 1. the symbols used for timing specif ications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t usixkh symbolizes usb timing (us) for the input (i) to go invalid (x) with respect to the time the usb clock reference (k) goes high (h). also, t uskhox symbolizes usb timing (us) for the us clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to usb clock. 3. all signals are measured from nvdd/2 of the rising edge of usb clock to 0.4 ? nvdd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurements, the hi-z or o ff-state is defined to be when the total current delivered thr ough the component pin is less than or equal to the leakage current specification. table 40. usb general timing parameters (continued) parameter symbol 1 min max unit note output z 0 = 50 ? nvdd/2 r l = 50 ? output signals t uskhov usbdr_clk input signals t usixkh t usivkh t uskhox
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 39 local bus this table provides the usb clock input (usb_clk_in) ac ti ming specifications. 11 local bus this section describes the dc and ac electrical specifications for the local bus interface of the mpc8314e. 11.1 local bus dc electrical characteristics this table provides the dc electrical characteristics for the local bus interface. 11.2 local bus ac electrical specifications this table describes the general timing parameters of the local bus interface of the mpc8314e. table 41. usb_clk_in dc electrical characteristics parameter symbol min max unit input high voltage v ih 2.7 nv dd +0.3 v input low voltage v il ?0.3 0.4 v table 42. usb_clk_in ac timing specifications parameter/condition conditions symbol min typical max unit frequency range ? f usb_clk_in ?24?mhz clock frequency tolerance ? t clk_tol ?0.005 0 0.005 % reference clock duty cycle measured at 1.6 v t clk_duty 40 50 60 % total input jitter/time interval error peak to peak value measured with a second order high-pass filter of 500 khz bandwidth t clk_pj ??200ps table 43. dc electrical characteristics (when operating at 3.3 v) parameter symbol min max unit output high voltage (nvdd = min, i oh = ?2 ma) v oh nvdd ? 0.2 ? v output low voltage (nvdd = min, i ol = 2 ma) v ol ?0 . 2v input high voltage v ih 2nvdd + 0.3 v input low voltage v il ?0.3 0.8 v input high current (v in = 0 v or v in = nvdd) i in ? 5 ? a table 44. local bus general timing parameters parameter symbol 1 min max unit note local bus cycle time t lbk 15 ? ns 2 input setup to lo cal bus clock t lbivkh 7 ? ns 3, 4
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 40 freescale semiconductor local bus this figure provides the ac te st load for the local bus. figure 23. local bus ac test load input hold from local bus clock t lbixkh 1.0 ? ns 3, 4 lale output fall to lad output transition (latch hold time) t lbotot1 1.5 ? ns 5 lale output fall to lad output transition (latch hold time) t lbotot2 3?n s6 lale output fall to lad output transition (latch hold time) t lbotot3 2.5 ? ns 7 local bus clock to output valid t lbkhov ?3n s3 local bus clock to output high impedance for lad t lbkhoz ?4n s8 lale output rise to lclk negative edge t lalehov ?3 . 0n s note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to falling edge of lclk0 (for all outputs and for lgta and lupwait inputs) or rising edge of lclk0 (for all other inputs). 3. all signals are measured from nvdd/2 of the rising/falling edge of lclk0 to 0.4 ? nvdd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. t lbotot1 should be used when rcwh[lale] is not set and the load on lale output pin is at least 10pf less than the load on lad output pins. 6. t lbotot2 should be used when rcwh[lale] is set and the load on la le output pin is at least 10pf less than the load on lad output pins. 7. t lbotot3 should be used when rcwh[lale] is set and the load on lale output pin equals to the load on lad output pins. 8. for active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. table 44. local bus general timing parameters (continued) parameter symbol 1 min max unit note output z 0 = 50 ? nvdd/2 r l = 50 ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 41 local bus figure 24 through figure 26 show the local bus signals. figure 24. local bus signals, nonspecial signals only figure 25. local bus signals, gpcm/u pm signals for lcrr[clkdiv] = 2 output signals: lbctl/lbcke/loe / t lbkhov t lbkhov lclk[n] input signals: lad[0:15] output signals: lad[0:15] t lbixkh t lbivkh t lbkhoz t lbotot lale input signal: lgta t lbixkh t lbivkh t lbixkh t lalehov lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 input signals: lad[0:15] upm mode output signals: lcs [0:3]/lbs [0:1]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov t lbkhov t lbkhoz
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 42 freescale semiconductor jtag figure 26. local bus signals, gpcm/u pm signals for lcrr[clkdiv] = 4 12 jtag this section describes the dc and ac electrical specifications for the ieee std 1149.1? (jtag) interface. 12.1 jtag dc electrical characteristics this table provides the dc electrical characteristics for the ieee 1149.1 (jtag) interface. table 45. jtag interface dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih ? 2.1 nvdd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in ?? 5 ? a output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 upm mode output signals: lcs [0:3]/lbs [0:1]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov t lbkhov t lbkhoz t2 t4 input signals: lad[0:15]
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 43 jtag 12.2 jtag ac timing specifications this section describes the ac el ectrical specifications for the ieee 1149.1 (jtag) interface. this table provides the jtag ac timing sp ecifications as defined in figure 28 through figure 31. table 46. jtag ac timing specific ations (independen t of sys_clk_in) 1 at recommended operating conditions (see ta b l e 2 ) parameter symbol 2 min max unit note jtag external clock frequency of operation f jtg 03 3 . 3m h z? jtag external clock cycle time t jtg 30 ? ns ? jtag external clock pulse width measured at 1.4 v t jtkhkl 15 ? ns ? jtag external clock rise and fall times t jtgr , t jtgf 02n s? trst assert time t trst 25 ? ns 3 input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 4 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 10 10 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 2 2 11 11 ns 5 output hold times: boundary-scan data tdo t jtkldx t jtklox 2 2 ? ? ns 5 jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 2 2 19 9 ns 5, 6 note: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- ?? load (see ta bl e 2 7 ). time-of-flight delays mu st be added for trace lengths, vias, and co nnectors in the system. 2. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. t rst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design and characterization.
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 44 freescale semiconductor jtag this figure provides the ac test load for t do and the boundary-scan outputs of the mpc8314e. figure 27. ac test load for the jtag interface this figure provides the jtag clock input timing diagram. figure 28. jtag clock input timing diagram this figure provides the trst timing diagram. figure 29. trst timing diagram this figure provides the boundary-scan timing diagram. figure 30. boundary-scan timing diagram output z 0 = 50 ? nvdd/2 r l = 50 ? jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (nvdd/2) trst vm = midpoint voltage (nvdd/2) vm vm t trst vm = midpoint voltage (nvdd/2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 45 i 2 c this figure provides the test access port timing diagram. figure 31. test access port timing diagram 13 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interface of the mpc8314e. 13.1 i 2 c dc electrical characteristics this table provides the dc electrical characteristics for the i 2 c interface. table 47. i 2 c dc electrical characteristics at recommended operating conditions with nvdd of 3.3 v 300 mv parameter symbol min max unit note input high voltage level v ih 0.7 ? nvdd nvdd + 0.3 v ? input low voltage level v il ?0.3 0.3 ? nvdd v ? low level output voltage v ol 00.2 ? nvdd v 1 high level output voltage v oh 0.8 ? nvdd nvdd + 0.3 v ? output fall time from v ih (min) to v il (max) with a bus capacitance from 10 to 400 pf t i2klkv 20 + 0.1 ? c b 250 ns 2 pulse width of spikes which must be suppressed by the input filter t i2khkl 05 0n s3 capacitance for each i/o pin c i ?1 0p f? input current (0 v ? v in ?? nvdd) i in ? 5 ? a4 note: 1. output voltage (open drain or open collector) condition = 3 ma sink current. 2. c b = capacitance of one bus line in pf. 3. see the mpc8315e powerquicc ii pro integrated host processor family reference manual for information on the digital filter used. 4. i/o pins obstruct the sda and scl lines if nvdd is switched off. vm = midpoint voltage (nvdd/2) vm vm t jtivkh t jtixkh jtag external clock output data valid t jtklox t jtkloz t jtklov input data valid output data valid tdi, tms tdo tdo
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 46 freescale semiconductor i 2 c 13.2 i 2 c ac electrical specifications this table provides the ac timing parameters for the i 2 c interface. this figure provides the ac test load for the i 2 c. figure 32. i 2 c ac test load table 48. i 2 c ac electrical specifications all values refer to v ih (min) and v il (max) levels (see ta bl e 4 7 ) parameter symbol 1 min max unit scl clock frequency f i2c 0 400 khz low period of the scl clock t i2cl 1.3 ? ? s high period of the scl clock t i2ch 0.6 ? ? s setup time for a repeated start condition t i2svkh 0.6 ? ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 0.6 ? ? s data setup time t i2dvkh 100 ? ns data hold time: cbus compatible masters i 2 c bus devices t i2dxkl ? 0 2 ? 0.9 3 ? s fall time of both sda and scl signals t i2cf 4 ? 300 ns setup time for stop condition t i2pvkh 0.6 ? ? s bus free time between a stop and start condition t i2khdx 1.3 ? ? s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ? nvdd ? v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ? nvdd ? v note: 1. the symbols used for timing specif ications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that th e data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to th e stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. mpc8314e provides a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. 3. the maximum t i2dvkh has to be met only if the device does not stretch the low period (t i2cl ) of the scl signal. 4. mpc8314e does not follow the i2c-bus specifications version 2.1 regarding the ti2cf ac parameter. output z 0 = 50 ? nvdd/2 r l = 50 ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 47 pci this figure shows the ac timing diagram for the i 2 c bus. figure 33. i 2 c bus ac timing diagram 14 pci this section describes the dc a nd ac electrical specifications for the pci bus of the mpc8314e. 14.1 pci dc electrical characteristics this table provides the dc electrical characteristics for the pci interface. 14.2 pci ac electrical specifications this section describes the general ac timing parame ters of the pci bus. note that the pci_clk or pci_sync_in signal is used as th e pci input clock depending on whet her the mpc8314e is configured as a host or agent device. this table shows th e pci ac timing specific ations at 66 mhz. . table 49. pci dc electrical characteristics 1 parameter symbol test condition min max unit high-level input voltage v ih v out ?? v oh (min) or 0.5 x nvdd nvdd + 0.3 v low-level input voltage v il v out ? v ol (max) ?0.5 0.3 ? nvdd v high-level output voltage v oh nvdd = min, i oh = ?500 ? a 0.9 x nvdd ? v low-level output voltage v ol nvdd = min, i ol = 1500 ? a ? 0.1 x nvdd v input current i in 0 v ?? v in ?? nvdd ? 10 ? a note: 1. the symbol v in , in this case, represents the nv in symbol referenced in ta bl e 1 and ta b l e 2 . table 50. pci ac timing specifications at 66 mhz parameter symbol 1 min max unit note clock to output valid t pckhov ?6 . 0n s2 output hold from clock t pckhox 1?n s2 clock to output high impedance t pckhoz ?1 4n s2 , 3 input setup to clock t pcivkh 3.3 ? ns 2, 4 sr s sda scl t i2cf t i2sxkl t i2cl t i2ch t i2dxkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh t i2cr t i2cf ps
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 48 freescale semiconductor pci this table shows the pci ac timing specifications at 33 mhz. this figure provides the ac test load for pci. figure 34. pci ac test load input hold from clock t pcixkh 0 ? ns 2, 4 note: 1. note that the symbols used for timing spec ifications herein fo llow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relati ve to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.3 local bus specifications . 3. for purposes of active/float timing meas urements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or eq ual to the leakage current specification. 4. input timings are measured at the pin. table 51. pci ac timing specifications at 33 mhz parameter symbol 1 min max unit note clock to output valid t pckhov ?1 1n s2 output hold from clock t pckhox 2?n s2 clock to output high impedance t pckhoz ?1 4n s2 , 3 input setup to clock t pcivkh 4.0 ? ns 2, 4 input hold from clock t pcixkh 0 ? ns 2, 4 note: 1. note that the symbols used for timing specifications follo w the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relati ve to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.3 local bus specifications . 3. for purposes of active/float timing meas urements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or eq ual to the leakage current specification. 4. input timings are measured at the pin. table 50. pci ac timing specifications at 66 mhz (continued) parameter symbol 1 min max unit note output z 0 = 50 ? nvdd/2 r l = 50 ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 49 high-speed serial interfaces (hssi) this figure shows the pci input ac timing conditions. figure 35. pci input ac timing measurement conditions this figure shows the pci output ac timing conditions. figure 36. pci output ac timing measurement condition 15 high-speed serial interfaces (hssi) this section describes the common portion of serdes dc electrical specifications, which is the dc requirement for serdes reference cl ocks. the serdes data lane?s tr ansmitter and receiver reference circuits are also shown. 15.1 signal terms definition the serdes utilizes differential sign aling to transfer data across the serial link. this section defines terms used in the description and specif ication of differential signals. figure 37 shows how the signals are defi ned. for illustration purpose, only one serdes lane is used for description. the figure shows waveform for either a tran smitter output (txn and txn ) or a receiver input (rxn and rxn ). each signal swings between a volts and b volts where a > b. using this waveform, the definitions are as follows. to simplify il lustration, the following definitions assume that the serdes transmitter and receiver operate in a fully symmetrical differential signaling environment. 1. single-ended swing the transmitter output signals and the receiver input signals txn, txn , rxn and rxn each have a peak-to-peak swing of a ? b volts. this is al so referred as each signal wire?s single-ended swing. 2. differential output voltage, v od (or differential output swing ): t pcivkh clk input t pcixkh clk output delay t pckhov high-impedance t pckhoz output t pckhox
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 50 freescale semiconductor high-speed serial interfaces (hssi) the differential output voltage (o r swing) of the transmitter, v od , is defined as th e difference of the two complimentary output voltages: v txn ? v txn . the v od value can be either positive or negative. 3. differential input voltage, v id (or differential input swing ): the differential input voltage (or swing) of the receiver, v id , is defined as the difference of the two complimentary input voltages: v rxn ? v rxn . the v id value can be either positive or negative. 4. differential peak voltage , v diffp the peak value of the differential transmitter output signal or the di fferential receiver input signal is defined as differential peak voltage, v diffp = |a ? b| volts. 5. differential peak-to-peak , v diffp-p because the differential output signal of the tran smitter and the differenti al input signal of the receiver each range from a ? b to ?(a ? b) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage, v diffp-p = 2*v diffp = 2 * |(a - b)| volts, which is twice of differential swing in amplitude, or twic e of the differential pe ak. for example, the output differential peak-peak voltage can also be calculated as v tx-diffp-p = 2*|v od |. 6. differential waveform the differential waveform is constructe d by subtracting the inverting signal (txn , for example) from the non-inverting signal (txn, fo r example) within a differential pair. there is only one signal trace curve in a differential waveform. the voltage represented in the differential waveform is not referenced to ground. refer to figure 46 as an example for differential waveform. 7. common mode voltage, v cm the common mode voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange ci rcuit and ground. in this ex ample, for serdes output, v cm_out = (v txn + v txn )/2 = (a + b) / 2, which is the arithmetic mean of the two compli mentary output voltages within a differential pair. in a system, the common mode voltage may often differ from one component?s output to the other?s input. sometimes, it may be even different between the receiver input and driver output circuits within the same component. it?s also referre d as the dc offset in some occasion.
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 51 high-speed serial interfaces (hssi) figure 37. differential voltage definitions for transmitter or receiver to illustrate these definitions using real values, consider the case of a cml (current mode logic) transmitter that has a common mode voltage of 2.25 v and each of its outputs, td and td , has a swing that goes between 2.5v and 2.0v. using these values, th e peak-to-peak voltage sw ing of each signal (td or td ) is 500 mv p-p, which is referred as the single-ended swing for each signal. in this example, since the differential signaling environmen t is fully symmetrical, the transmit ter output?s differential swing (v od ) has the same amplitude as each signal?s single- ended swing. the differential output signal ranges between 500 mv and ?500 mv, in other words, v od is 500 mv in one phase and ?500 mv in the other phase. the peak differential voltage (v diffp ) is 500 mv. the peak-to-pe ak differential voltage (v diffp-p ) is 1000 mv p-p. 15.2 serdes reference clocks the serdes reference clock inputs are applied to an internal pll whose output creates the clock used by the corresponding serdes lanes. th e serdes reference clocks input is sd_ref_clk and sd_ref_clk for pci express and sgmii interface. the following sections describe the serdes re ference clock requirement s and some application information. 15.2.1 serdes reference clock receiver characteristics figure 38 shows a receiver reference diagram of the serdes reference clocks. ? the supply voltage requirements for xcorevdd are specified in table 1 and table 2 . ? serdes reference clock receiver reference circuit structure ? the sd_ref_clk and sd_ref_clk are internally ac-coupled di fferential inputs as shown in figure 38 . each differential clock i nput (sd_ref_clk or sd_ref_clk ) has a 50- ? termination to xcorevss foll owed by on-chip ac-coupling. ? the external reference clock driver mu st be able to drive this termination. ? the serdes reference clock input can be eith er differential or si ngle-ended. refer to the differential mode and single-e nded mode description below for further detailed requirements. differential swing, v id or v od = a - b a volts b volts txn or rxn txn or rxn differential peak voltage, v diffp = |a - b| differential peak-peak voltage, v diffpp = 2*v diffp (not shown) v cm = (a + b) / 2
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 52 freescale semiconductor high-speed serial interfaces (hssi) ? the maximum average current requirement that also determines the common mode voltage range ? when the serdes reference clock differential inputs are dc coupl ed externally with the clock driver chip, the maximum average current allowed for each input pi n is 8ma. in this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 ma (refer to the following bullet for mo re detail), since the input is ac-coupled on-chip. ? this current limitation sets the maximum comm on mode input voltage to be less than 0.4v (0.4v/50 = 8ma) while the mi nimum common mode input leve l is 0.1v above xcorevss. for example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0ma to 16ma (0-0.8v), such that each phase of the differential input has a single-ended swing from 0v to 800mv with the common mode voltage at 400mv. ? if the device driving the sd_ref_clk and sd_ref_clk inputs cannot drive 50 ohms to xcorevss dc, or it exceeds the maximum input current limitations, then it must be ac-coupled off-chip. ? the input amplitude requirement ? this requirement is described in detail in the following sections. figure 38. receiver of serdes reference clocks 15.2.2 dc level requirement for serdes reference clocks the dc level requirement for the mpc8315e serdes reference cloc k inputs is different depending on the signaling mode used to connect the clock driver ch ip and serdes reference clock inputs as described below. ? differential mode ? the input amplitude of the di fferential clock must be betw een 400mv and 1600m v differential peak-peak (or between 200mv and 800mv differential peak). in ot her words, each signal wire of the differential pair must have a singl e-ended swing less than 800mv and greater than 200mv. this requirement is th e same for both external dc-c oupled or ac-coupl ed connection. ? for external dc-coupled connection, as described in section 15.2.1, the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be input amp 50 ? 50 ? sd_ref_clk sd_ref_clk
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 53 high-speed serial interfaces (hssi) between 100 mv and 400 mv. figure 39 shows the serdes referenc e clock input requirement for dc-coupled connection scheme. ? for external ac-coupled connection, there is no common mode voltage requirement for the clock driver. since the external ac-coupling capacitor blocks th e dc level, the clock driver and the serdes reference clock receiver operate in different comma nd mode voltages. the serdes reference clock receiver in this connection scheme has its common mode voltage set to xcorevss. each signal wire of the differential inputs is allowed to swing below and above the common mode voltage (xcorevss). figure 40 shows the serdes re ference clock input requirement for ac-coupled connection scheme. ? single-ended mode ? the reference clock can al so be single-ended. the sd_ref_clk input amplitude (single-ended swing) must be between 400mv and 800mv peak-peak (from vmin to vmax) with sd_ref_clk either left unconnect ed or tied to ground. ? the sd_ref_clk input average volta ge must be between 200 and 400 mv. figure 41 shows the serdes reference clock input requirement for single-ended signaling mode. ? to meet the input amplitude requirement, the re ference clock inputs might need to be dc or ac-coupled externally. for the be st noise performance, the reference of the clock could be dc or ac-coupled into the unused phase (sd_ref_clk ) through the same source impedance as the clock input (sd_ref_clk) in use. figure 39. differential reference clock input dc requirements (external dc-coupled) figure 40. differential reference clock input dc requirements (external ac-coupled) sd_ref_clk sd_ref_clk vmax < 800 mv vmin > 0 v 100 mv < vcm < 400 mv 200 mv < input amplitude or differential peak < 800 mv sd_ref_clk sd_ref_clk vcm 200 mv < input amplitude or differential peak < 800 mv vmax < vcm + 400 mv vmin > vcm ? 400 mv
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 54 freescale semiconductor high-speed serial interfaces (hssi) figure 41. single-ended reference clock input dc requirements 15.2.3 interfacing with other differential signaling levels with on-chip termination to xcorevss, the differen tial reference clocks in puts are hcsl (high-speed current steering logic) compatible dc-coupled. many other low voltage differential type outputs like lvds (low voltage differenti al signaling) can be used but may need to be ac-coupled due to the limited common mode input range allowed (100 to 400 mv) for dc-coupled connection. lvpecl outputs can produce signal with too large am plitude and may need to be dc-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to ac-coupling. note figure 42 ? figure 45 are for conceptual reference only. due to the fact that clock driver chip's internal struct ure, output impedan ce and termination requirements are different between vari ous clock driver chip manufacturers, it?s very possible that the clock circ uit reference designs provided by clock driver chip vendor are diff erent from what is shown below. they might also vary from one vendor to the other. therefore, freescale semiconductor can neither provide the optimal clock driver reference circuits , nor guarantee the correctness of the following clock driver connection reference circuits. the system designer is recommended to cont act the selected clock driver chip vendor for the optimal reference ci rcuits with the mpc8315e serdes reference clock receiver requireme nt provided in this document. sd_ref_clk sd_ref_clk 400 mv < sd_ref_clk input amplitude < 800 mv 0v
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 55 high-speed serial interfaces (hssi) this figure shows the serdes reference clock connection reference circuits for hcsl type clock driver. it assumes that the dc levels of the clock driver chip is compatible wi th mpc8315e serdes reference clock input?s dc requirement. figure 42. dc-coupled differential connecti on with hcsl clock driver (reference only) this figure shows the serdes reference clock connection reference ci rcuits for lvds type clock driver. since lvds clock driver?s common mode voltage is higher than the mpc8315e serdes reference clock input?s allowed range (100 to 400mv), ac-coupled c onnection scheme must be used. it assumes the lvds output driver features 50- ?? termination resistor. it also a ssumes that the lvds transmitter establishes its own common mode level without rely ing on the receiver or ot her external component. figure 43. ac-coupled differenti al connection with lvds clock driver (reference only) figure 44 shows the serdes reference clock connection refe rence circuits for lvpecl type clock driver. since lvpecl driver?s dc levels (both common mode voltages and output swing) are incompatible with mpc8315e serdes reference clock input?s dc requirement, ac-coupling has to be used. figure 44 50 ? 50 ? sd_ref_clk sd_ref_clk clock driver 100 ?? differential pwb trace clock driver vendor dependent source termination resistor serdes refer. clk receiver clock driver clk_out clk_out hcsl clk driver chip 33 ? 33 ? total 50 ??? assume clock driver?s output impedance is about 16 ?? mpc8315e clk_out 50 ? 50 ? sd_ref_clk sd_ref_clk clock driver 100 ?? differential pwb trace serdes refer. clk receiver clock driver clk_out clk_out lvds clk driver chip 10 nf 10 nf mpc8315e
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 56 freescale semiconductor high-speed serial interfaces (hssi) assumes that the lvpecl clock driver?s output impedance is 50 ??? r1 is used to dc-bias the lvpecl outputs prior to ac-co upling. its value coul d be ranged from 140 ?? to 240 ?? depending on clock driver vendor?s requirement. r2 is used together wi th the serdes reference clock receiver?s 50- ? termination resistor to attenuate the lvpecl out put?s differential peak level such that it meets the mpc8315e serdes reference clock?s differential input amplitude requirement (between 200mv and 800mv differential peak). for example, if the lvpecl output?s differential peak is 900mv and th e desired serdes reference clock input amplitude is selected as 600mv, the attenuation factor is 0.67, which requires r2 = 25 ??? please consult clock driver chip manufacturer to verify wh ether this connection scheme is compatible with a particular clock driver chip. figure 44. ac-coupled differential connection with lvpecl clock driver (reference only) this figure shows the serdes refere nce clock connection reference circui ts for a single-ended clock driver. it assumes the dc levels of the clock driver are compatible with mpc8315e serdes reference clock input?s dc requirement. figure 45. single-ended connection (reference only) 50 ? 50 ? sd_ref_clk sd_ref_clk clock driver 100 ?? differential pwb trace serdes refer. clk receiver clock driver clk_out clk_out lvpecl clk driver chip r2 r2 r1 mpc8315e r1 10 nf 10 nf 50 ? 50 ? sd_ref_clk sd_ref_clk 100 ?? differential pwb trace serdes refer. clk receiver clock driver clk_out single-ended clk driver chip mpc8315e 33 ? total 50 ??? assume clock driver?s output impedance is about 16 ?? 50 ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 57 high-speed serial interfaces (hssi) 15.2.4 ac requirements for serdes reference clocks the clock driver selected should provide a high qua lity reference clock wi th low phase noise and cycle-to-cycle jitter. phas e noise less than 100khz can be tracked by the pll and data recovery loops and is less of a problem. phase noise a bove 15mhz is filtered by the pll. the most pr oblematic phase noise occurs in the 1-15mhz range. the source impedance of the clock driver should be 50 ? to match the transmission line and reduce reflections whic h are a source of noise to the system. this table describes some ac parameters common to sgmii and pci express protocols. figure 46. differential measurement points for rise and fall time table 52. serdes reference clock common ac parameters at recommended operating conditions with xcorevdd= 1.0v 5% parameter symbol min max unit note rising edge rate rise edge rate 1.0 4.0 v/ns 2, 3 falling edge rate fall edge rate 1.0 4.0 v/ns 2, 3 differential input high voltage v ih +200 ? mv 2 differential input low voltage v il ? ?200 mv 2 rising edge rate (sdn_ref_clk) to falling edge rate (sdn_ref_clk ) matching rise-fall matching ?20%1, 4 note: 1. measurement taken from single ended waveform. 2. measurement taken from differential waveform. 3. measured from -200 mv to +200 mv on the differenti al waveform (derived from sdn_ref_clk minus sdn_ref_clk ). the signal must be monotonic through the measurement region for rise and fall time. the 400 mv measurement window is centered on the differential zero crossing. see figure 46 . 4. matching applies to rising edge rate for sdn_ref_clk and falling edge rate for sdn_ref_clk . it is measured using a 200 mv window centered on the median cross poi nt where sdn_ref_clk rising meets sdn_ref_clk falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. the rise edge rate of sdn_ref_clk should be compared to the fall edge rate of sdn_ref_clk , the maximum allowed difference should not exceed 20% of the slowest edge rate. see figure 47 . v ih = +200 v il = ?200 0.0 v sdn_ref_cl k minus
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 58 freescale semiconductor high-speed serial interfaces (hssi) figure 47. single-ended measurement points for rise and fall time matching the other detailed ac requirements of the serdes reference clocks is defined by each interface protocol based on application usage. refer to the following sections for detailed information: ? section 9.5.2, ?ac requirements for sg mii sd_ref_clk and sd_ref_clk ? ? section 16.2, ?ac requirements fo r pci express serdes clocks ? 15.2.4.1 spread spectrum clock sd_ref_clk/sd_ref_clk are not intended to be used with, and should not be clocked by, a spread spectrum clock source. 15.3 serdes transmitter and receiver reference circuits this figure shows the reference circuits for se rdes data lane?s transmitter and receiver. figure 48. serdes transmitter a nd receiver reference circuits the dc and ac specification of serdes data lanes are defined in each interface protocol section below (pci express or sgmii) in this doc ument based on the application usage: ? section 9.5, ?sgmii interface electrical characteristics ? ? section 16, ?pci express ? note that external ac c oupling capacitor is required for the above two serial transmission protocols with the capacitor value defined in specifi cation of each protocol section. sdn_ref_clk sdn_ref_clk sdn_ref_clk sdn_ref_clk 50 ? 50 ? receiver transmitter tx n txn rxn rx n 50 ? 50 ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 59 pci express 16 pci express this section describes the dc and ac electrical specifications for th e pci express bus of the mpc8315e. 16.1 dc requirements for pc i express sd_ref_clk and sd_ref_clk for more information, see section 15.2, ?serdes reference clocks .? 16.2 ac requirements for pci express serdes clocks this table lists the pci expres s serdes clock ac requirements. 16.3 clocking dependencies the ports on the two ends of a link mu st transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. this is specified to al low bit rate clock sources with a 300 ppm tolerance. 16.4 physical layer specifications following is a summary of the speci fications for the physical layer of pci express on this device. for further details as well as the specifications of the transport and data link layer please use the pci express base specification , rev. 1.0a. 16.4.1 differential transmitter (tx) output this table defines the specif ications for the differential output at all transmitters (txs). the parameters are specified at the component pins. table 53. sd_ref_clk and sd_ref_clk ac requirements symbol parameter description min typ max unit note t ref refclk cycle time ? 10 ? ns ? t refcj refclk cycle-to-cycle jitt er. difference in the per iod of any two adjacent refclk cycles. ??100ps ? t refpj phase jitter. deviation in edge location with respect to mean edge location. ?50 ? 50 ps ? table 54. differential transmitter (tx) output specifications parameter symbol comments min typical max unit note unit interval ui each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. 399.88 400 400.12 ps 1 differential peak-to-peak output voltage v tx-diffp-p v tx-diffp-p = 2*|v tx-d+ - v tx-d- | 0.8 ? 1.2 v 2
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 60 freescale semiconductor pci express de-emphasized differential output voltage (ratio) v tx-de-ratio ratio of the v tx-diffp-p of the second and following bits after a transition divided by the v tx-diffp-p of the first bit after a transition. ?3.0 ?3.5 -4.0 db 2 minimum tx eye width t tx-eye the maximum transmitter jitter can be derived as t tx-max-jitter = 1 - u tx-eye = 0.3 ui. 0.70 ? ? ui 2, 3 maximum time between the jitter median and maximum deviation from the median t tx-eye-median-to- max-jitter jitter is defined as the measurement variation of the crossing points (v tx-diffp-p = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. ? ? 0.15 ui 2, 3 d+/d- tx output rise/fall time t tx-rise , t tx-fall ?0 . 1 2 5 ? ? u i 2 , 5 rms ac peak common mode output voltage v tx-cm-acp v tx-cm-acp = rms(|v txd+ + v txd- |/2 - v tx-cm-dc ) v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d- |/2 ??20mv2 absolute delta of dc common mode voltage during l0 and electrical idle v tx-cm-dc- active- idle-delta |v tx-cm-dc (during l0) - v tx-cm-idle-dc (during electrical idle) |<=100 mv v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d- |/2 [l0] v tx-cm-idle-dc = dc (avg) of |v tx-d+ + v tx-d- |/2 [electrical idle] 0 ? 100 mv 2 absolute delta of dc common mode between d+ and d? v tx-cm-dc-line-delta |v tx-cm-dc-d+ - v tx-cm-dc-d- | <= 25 mv v tx-cm-dc-d+ = dc (avg) of |v tx-d+ | v tx-cm-dc-d- = dc (avg) of |v tx-d- | 0?25mv2 electrical idle differential peak output voltage v tx-idle-diffp v tx-idle-diffp = |v tx-idle-d+ -v tx-idle-d- | <= 20 mv 0?20mv2 amount of voltage change allowed during receiver detection v tx-rcv-detect the total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. ? ? 600 mv 6 tx dc common mode voltage v tx-dc-cm the allowed dc common mode voltage under any conditions. ??3.6v6 tx short circuit current limit i tx-short the total current the transmitter can provide when shorted to its ground ??90ma? minimum time spent in electrical idle t tx-idle-min minimum time a transmitter must be in electrical idle utilized by the receiver to start looking for an electrical idle exit after successfully receiving an electrical idle ordered set 50 ? ? ui ? table 54. differential transmitter (tx) output specifications (continued) parameter symbol comments min typical max unit note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 61 pci express maximum time to transition to a valid electrical idle after sending an electrical idle ordered set t tx-idle-set-to-idle after sending an electrical idle ordered set, the transmitter must meet all electrical idle specifications within this time. this is considered a debounce time for the transmitter to meet electrical idle after transitioning from l0. ??20ui? maximum time to transition to valid tx specifications after leaving an electrical idle condition t tx-idle-to-diff-data maximum time to meet all tx specifications when transitioning from electrical idle to sending differential data. this is considered a debounce time for the tx to meet all tx specifications after leaving electrical idle ??20ui? differential return loss rl tx-diff measured over 50 mhz to 1.25 ghz. 12 ? ? db 4 common mode return loss rl tx-cm measured over 50 mhz to 1.25 ghz. 6 ? ? db 4 dc differential tx impedance z tx-diff-dc tx dc differential mode low impedance 80 100 120 ? ? transmitter dc impedance z tx-dc required tx d+ as well as d- dc impedance during all states 40 ? ? ? ? lane-to-lane output skew l tx-skew static skew between any two transmitter lanes within a single link ? ? 500 + 2 ui ps ? ac coupling capacitor c tx all transmitters shall be ac coupled. the ac coupling is required either within the media or within the transmitting component itself. 75 ? 200 nf 8 crosslink random timeout t crosslink this random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one downstream and one upstream port. 0?1ms7 note: 1. no test load is necessarily associated with this value. 2. specified at the measurement point into a timing and voltage compliance test load as shown in figure 51 and measured over any 250 consecutive tx uis. (also refer to the transmitter compliance eye diagram shown in figure 49 .) 3. a t tx-eye = 0.70 ui provides for a total sum of deterministic and random jitter budget of t tx-jitter-max = 0.30 ui for the transmitter collected over any 250 consecutive tx uis. the t tx-eye-median-to-max-jitter median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median de scribes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value . 4. the transmitter input impedance shall result in a differential return loss greater than or equal to 12 db and a common mode r eturn loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all val id input levels. the reference impedance for return loss measurements is 50 ? to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50- ? probes, see figure 51 ). note that the series capacitors, c tx , is optional for the return loss measurement. 5. measured between 20%?80% at transmitter package pins into a test load as shown in figure 51 for both v tx-d+ and v tx-d- . 6. see section 4.3.1.8 of the pci express base specifications , rev 1.0a. 7. see section 4.2.6.3 of the pci express base specifications , rev 1.0a. 8. mpc8315e serdes transmitter does not have c tx built-in. an external ac coupling capacitor is required table 54. differential transmitter (tx) output specifications (continued) parameter symbol comments min typical max unit note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 62 freescale semiconductor pci express 16.4.2 transmitter compliance eye diagrams the tx eye diagram in figure 49 is specified using the passive compliance/test measurement load (see figure 51 ) in place of any real pci express interconnect + rx component. there are two eye diagrams that must be met for the transmitter. both diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. the different eye diag rams differ in voltage depending on whether it is a transition bit or a de-emphasized bit. the exact reduced voltage level of the de-emphasized bit is always relative to the transition bit. the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calc ulated over 3500 consecutive unit intervals of sample data. the eye diagram is created using all edge s of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note it is recommended that the recovered tx ui be calculated using all edges in the 3500 consecutive ui interval with a fit algorithm us ing a minimization merit function (that is, least squa res and median deviation fits). figure 49. minimum transmitter timing and voltage output compliance specifications [de-emphasized bit] 566 mv (3 db) >= v tx-diffp-p-min >= 505 mv (4 db) [transition bit] v tx-diffp-p-min = 800 mv [transition bit] v tx-diffp-p-min = 800 mv 0.7 ui = ui ? 0.3 ui(j tx-total-max ) v tx-diff = 0 mv (d+ d? crossing point) v tx-diff = 0 mv (d+ d? crossing point)
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 63 pci express 16.4.3 differential receiver (rx) input specifications this table defines the specifications for the differential input at all r eceivers (rxs). the parameters are specified at the component pins. table 55. differential receiver (rx) input specifications parameter symbol comments min typical max unit note unit interval ui each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. 399.88 400 400.12 ps 1 differential peak-to-peak output voltage v rx-diffp-p v rx-diffp-p = 2*|v rx-d+ - v rx-d- | 0.175 ? 1.200 v 2 minimum receiver eye width t rx-eye the maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as t rx-max-jitter = 1 - u rx-eye = 0.6 ui. 0.4 ? ? ui 2, 3 maximum time between the jitter median and maximum deviation from the median. t rx-eye-median-to-max-ji tter jitter is defined as the measurement variation of the crossing points (v rx-diffp-p = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. ? ? 0.3 ui 2, 3, 7 ac peak common mode input voltage v rx-cm-acp v rx-cm-acp = |v rxd+ + v rxd- |/2 - v rx-cm-dc v rx-cm-dc = dc (avg) of |v rx-d+ + v rx-d- |/2 ??150mv2 differential return loss rl rx-diff measured over 50 mhz to 1.25 ghz with the d+ and d- lines biased at +300 mv and -300 mv, respectively. 15 ? ? db 4 common mode return loss rl rx-cm measured over 50 mhz to 1.25 ghz with the d+ and d- lines biased at 0 v. 6??db4 dc differential input impedance z rx-diff-dc rx dc differential mode impedance. 80 100 120 ? 5 dc input impedance z rx-dc required rx d+ as well as d- dc impedance (50 20% tolerance). 40 50 60 ? 2, 5
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 64 freescale semiconductor pci express powered down dc input impedance z rx-high-imp-dc required rx d+ as well as d- dc impedance when the receiver terminations do not have power. 200 k ? ? ? 6 electrical idle detect threshold v rx-idle-det-diffp-p v peeidt = 2*|v rx-d+ -v rx-d- | measured at the package pins of the receiver 65 ? 175 mv ? unexpected electrical idle enter detect threshold integration time t rx-idle-det-diff- entertime an unexpected electrical idle (vrx-diffp-p < vrx-idle-det-diffp-p) must be recognized no longer than trx-idle-det-diff-entertime to signal an unexpected idle condition. ??10ms? to t a l s k e w l rx-skew skew across all lanes on a link. this includes variation in the length of skp or dered set (e.g. com and one to five skp symbols) at the rx as well as any delay differences arising from the interconnect itself. ? ? 20 ns ? note: 1. no test load is necessarily associated with this value. 2. specified at the measurement po int and measured over any 250 consecutive uis. the test load in figure 51 should be used as the rx device when taking measurements (also refer to the receiver compliance eye diagram shown in figure 50 ). if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 3. a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui determinis tic and random jitter budget for the transmitter and interconnect collected any 250 consecutive uis. the t rx-eye-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. ui jitter b udget collected over any 250 consecutive t x uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. if the clocks to the rx and tx are n ot derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. 4. the receiver input impedance shall result in a differential return loss greater than or equal to 15 db with the d+ line biase d to 300 mv and the d? line biased to ?300 mv and a common mode return loss greater than or equal to 6 db (no bias required) over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements for is 50 ? to ground for both the d+ and d? line (that is, as measured by a vector network analyzer with 50- ? probes, see figure 51 ). note that the series capacitors, c tx , is optional for the return loss measurement. 5. impedance during all ltssm states. when transitioning from a f undamental reset to detect (the initial state of the ltssm) the re is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 6. the rx dc common mode impedance that exists when no power is present or fundamental reset is asserted. this helps ensure that the receiver detect circuit does not falsely assume a receiv er is powered on when it is not. this term must be measured at 300 mv above the rx ground. 7. it is recommended that the recovered tx ui is calculated us ing all edges in the 3500 consecutive ui interval with a fit algor ithm using a minimization merit function. least squares and median devi ation fits have worked well with experimental and simulated d ata. table 55. differential receiver (r x) input specifications (continued) parameter symbol comments min typical max unit note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 65 pci express 16.5 receiver compliance eye diagrams the rx eye diagram in figure 50 is specified using the passive comp liance/test measurement load (see figure 51 ) in place of any real pci express rx component. in general, th e minimum receiver eye diagram measured with the compliance /test measurement load (see figure 51 ) is larger than th e minimum receiver eye diagram measured over a range of systems at th e input receiver of any re al pci express component. the degraded eye diagram at the input receiver is due to traces internal to the p ackage as well as silicon parasitic characteristics which cause the real pci express compone nt to vary in impedance from the compliance/test m easurement load. the input receiver eye diag ram is implementation specific and is not specified. rx component designer s hould provide additional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in figure 50 ) expected at the input receiver based on an adequate combination of system simulations and the return loss measured looking into the rx package and silicon. the rx eye diagra m must be aligned in time using the jitter median to locate the center of the eye diagram. the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calc ulated over 3500 consecutive unit intervals of sample data. the eye diagram is created using all edge s of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note the reference impedance for re turn loss measurements is 50 ? to ground for both the d+ and d- line (t hat is, as measured by a vector network analyzer with 50 ? probes?see figure 51 ). note that the series capacitors, c peacctx , are optional for the return loss measurement. figure 50. minimum receiver eye timing and voltage compliance specification 16.5.1 compliance test and measurement load the ac timing and voltage parameters must be verified at the measur ement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in figure 51 . v rx-diffp-p-min > 175 mv 0.4 ui = t rx-eye-min v rx-diff = 0 mv (d+ d? crossing point) v rx-diff = 0 mv (d+ d? crossing point)
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 66 freescale semiconductor timers note the allowance of the measurement poin t to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from d+ and d? not being exactly matched in lengt h at the package pin boundary. figure 51. compliance test/measurement load 17 timers this section describes the dc a nd ac electrical specifications for the timers of the mpc8314e. 17.1 timers dc electrical characteristics this table provides the dc electrical characteri stics for the timers pins , including tin, tout , tgate , and rtc_clk. 17.2 timers ac timing specifications this table provides the timers input and output ac timing specifications. table 56. timers dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ? 2.1 nvdd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in 0 v ?? v in ?? nvdd ? 5 ? a table 57. timers input ac timing specifications characteristic symbol 1 min unit timers inputs?minimum pulse width t tiwid 20 ns
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 67 gpio this figure provides the ac test load for the timers. figure 52. timers ac test load 18 gpio this section describes the dc a nd ac electrical specifications for the gpio of the mpc8314e. 18.1 gpio dc electrical characteristics this table provides the dc electrical characteristics for the gpio. 18.2 gpio ac timing specifications this table provides the gpio input and output ac timing specifications. note: 1. timers inputs and outputs are asynchronous to any visible cl ock. timers outputs should be synchronized before use by any external synchronous logic. timers input are required to be valid for at least t tiwid ns to ensure proper operation. table 58. gpio dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ? 2.1 nvdd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in 0 v ?? v in ?? nvdd ? 5 ? a table 59. gpio input ac timing specifications characteristic symbol 1 min unit gpio inputs?minimum pulse width t piwid 20 ns note: 1. gpio inputs and outputs are asynchronous to any visible cloc k. gpio outputs should be synchronized before use by any external synchronous logic. gpio inputs are required to be valid for at least t piwid ns to ensure proper operation. table 57. timers input ac timing specifications characteristic symbol 1 min unit output z 0 = 50 ? nvdd/2 r l = 50 ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 68 freescale semiconductor ipic this figure provides the ac test load for the gpio. figure 53. gpio ac test load 19 ipic this section describes the dc and ac electrical specifications for the external interrupt pins of the mpc8314e. 19.1 ipic dc electrical characteristics this table provides the dc electrical charac teristics for the external interrupt pins. 19.2 ipic ac timing specifications this table provides the ipic input and output ac timing specifications. 20 spi this section describes the dc and ac electric al specifications for the spi of the mpc8314e. table 60. ipic dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih ? 2.1 nvdd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in ?? 5 ? a output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v table 61. ipic input ac timing specifications characteristic symbol 1 min unit ipic inputs?minimum pulse width t piwid 20 ns note: 1. ipic inputs and outputs are asynchronous to any visible clock. ipic outputs should be synchronized before use by any external synchronous logic. ipic inputs are required to be valid for at least t piwid ns to ensure proper operation when working in edge triggered mode. output z 0 = 50 ? nvdd/2 r l = 50 ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 69 spi 20.1 spi dc electrical characteristics this table provides the dc electrical characteristics for the spi. 20.2 spi ac timing specifications this table and provide the spi input and output ac ti ming specifications. this figure provides the ac test load for the spi. figure 54. spi ac test load figure 55 and figure 56 represent the ac timing from table 63 . note that although the specifications generally reference the risi ng edge of the clock, these ac timing diag rams also apply when the falling edge is the active edge. table 62. spi dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih ? 2.1 nvdd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in ?? 5 ? a output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v table 63. spi ac timing specifications 1 characteristic symbol 2 min max unit spi outputs valid?master mode (internal clock) delay t nikhov ?6ns spi outputs hold?master mode (internal clock) delay t nikhox 0.5 ns spi outputs valid?slave mode (external clock) delay t nekhov ?8.5ns spi outputs hold?slave mode (external clock) delay t nekhox 2?ns spi inputs?master mode (interna l clock) input setup time t niivkh 6?ns spi inputs?master mode (internal clock)input hold time t niixkh 0?ns spi inputs?slave mode (external clock) input setup time t neivkh 4?ns spi inputs?slave mode (external clock) input hold time t neixkh 2?ns note: 1. output specifications ar e measured from the 50% level of the rising edge of spiclk to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t nikhox symbolizes the internal timing (ni) for the time spiclk clock reference (k) goes to the high state (h) until outputs (o) are invalid (x). output z 0 = 50 ? nvdd/2 r l = 50 ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 70 freescale semiconductor tdm this figure shows the spi timing in slave mode (external clock). figure 55. spi ac timing in slave mode (external clock) diagram this figure shows the sp i timing in master m ode (internal clock). figure 56. spi ac timing in master mode (internal clock) diagram 21 tdm this section describes the dc a nd ac electrical specifications for the tdm of the mpc8314e. 21.1 tdm dc electrical characteristics this table provides the dc electrical characteristics tdm. table 64. tdm dc electrical characteristics characteristic symbol condition min max unit output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v input high voltage v ih ? 2.1 nvdd + 0.3 v input low voltage v il ?? 0 . 30 . 8v input current i in 0 v ?? v in ?? nvdd ? 5 ? a spiclk (input) t neixkh t neivkh t nekhov input signals: spimosi (see note) output signals: spimiso (see note) note: the clock edge is selectable on spi. spiclk (output) t niixkh t nikhov input signals: spimiso (see note) output signals: spimosi (see note) note: the clock edge is selectable on spi. t niivkh
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 71 tdm 21.2 tdm ac electrical characteristics this table provides the td m ac timing specifications. this figure shows the td m receive signal timing. figure 57. tdm receive signals table 65. tdm ac timing specifications parameter/condition symbol min max unit tdmxrck/tdmxtck t dm 20.0 ? ns tdmxrck/tdmxtck high pulse width t dm_high 8.0 ? ns tdmxrck/tdmxtck low pulse width t dm_low 8.0 ? ns tdmxrck/tdmxtck rise time (20% to 80%) t dmkh 1.0 4.0 ns tdmxrck/tdmxtck fall time (80% to 20%) t dmkl 1.0 4.0 ns tdm all input setup time t dmivkh 3.0 ? ns tdmxrd hold time t dmrdixkh 3.5 ? ns tdmxtfs/tdmxrfs input hold time t dmfsixkh 2.0 ? ns tdmxtck high to tdmxtd output active t dm_outac 4.0 ? ns tdmxtck high to tdmxtd output valid t dmtkhov ? 14.0 ns tdmxtd hold time t dmtkhox 2.0 ? ns tdmxtck high to tdmxtd output high impedance t dm_outhi ? 10.0 ns tdmxtfs/tdmxrfs output valid t dmfskhov ? 13.5 ns tdmxtfs/tdmxrfs output hold time t dmfskhox 2.5 ? ns note: 1. the symbols used for timing specificat ions herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t tdmivkh symbolizes tdm timing (dm) with respect to the time the input signals (i) reach the valid state (v) relative to the tdm clock, t tc , reference (k) going to the high (h) state or setup time. also, output signals (o), hold (x). 2. output values are based on 30 pf capacitive load. 3. inputs are referenced to the sampling that the tdm is programmed to use. outputs are referenced to the programming edge they are programmed to use. use of the rising edge or fa lling edge as a reference is programmable. tdmxtck and tdmxrck are shown using the rising edge. tdmxrck tdmxrd tdmxrfs tdmxrfs (output) ~ ~ t dm t dm_high t dm_low t dmivkh t dmivkh t dmrdixkh t dmfsixkh t dmfskhov t dmfskhox
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 72 freescale semiconductor package and pin listings this figure shows the td m transmit signal timing. figure 58. tdm transmit signals 22 package and pin listings this section details package parameters, pin assignm ents, and dimensi ons. the mpc8314e is available in a thermally enhanced plastic ball grid array (tepbga ii), see section 22.1, ?package parameters for the mpc8314e tepbga ii,? and section 22.2, ?mechanical dime nsions of the tepbga ii,? for information on the tepbga ii. 22.1 package parameters for the mpc8314e tepbga ii the package parameters are as provided in the following list. the package type is 29 mm ? 29 mm, tepbga ii. package outline 29 mm ? 29 mm interconnects 620 pitch 1 mm module height (typical) 2.23 mm solder balls 96.5 sn/3.5 ag (vr package ) ball diameter (typical) 0.6 mm tdmxtck tdmxtd ~ ~ ~ ~ tdmxrck tdmxtfs (output) tdmxtfs (input) t dm t dm_high t dm_low t dmivkh t dm_outac t dmfsixkh t dmtkhov t dmtkhox t dm_outhi t dmfskhov t dmfskhox
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 73 package and pin listings 22.2 mechanical dimensions of the tepbga ii this figure shows the mech anical dimensions and bottom surface nomenclature of the 620-pin tepbga ii package. figure 59. mechanical dimensions and bottom surface nomenclature of the tepbga ii 22.3 pinout listings this table provides the pin-out li sting for the tepbga ii package. notes: 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is determined by the spherical crowns of the solder balls.
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 74 freescale semiconductor package and pin listings table 66. mpc8314e tepbga ii pinout listing signal package pin number pin type power supply note ddr memory controller interface memc_mdq[0] af16 i/o gvdd ? memc_mdq[1] ae17 i/o gvdd ? memc_mdq[2] ah17 i/o gvdd ? memc_mdq[3] ag17 i/o gvdd ? memc_mdq[4] ag18 i/o gvdd ? memc_mdq[5] ah18 i/o gvdd ? memc_mdq[6] ad18 i/o gvdd ? memc_mdq[7] af19 i/o gvdd ? memc_mdq[8] ah19 i/o gvdd ? memc_mdq[9] ad19 i/o gvdd ? memc_mdq[10] ag20 i/o gvdd ? memc_mdq[11] ah20 i/o gvdd ? memc_mdq[12] ah21 i/o gvdd ? memc_mdq[13] ae21 i/o gvdd ? memc_mdq[14] ah22 i/o gvdd ? memc_mdq[15] ad21 i/o gvdd ? memc_mdq[16] ag10 i/o gvdd ? memc_mdq[17] ah9 i/o gvdd ? memc_mdq[18] ah8 i/o gvdd ? memc_mdq[19] ad11 i/o gvdd ? memc_mdq[20] ah7 i/o gvdd ? memc_mdq[21] ag7 i/o gvdd ? memc_mdq[22] af8 i/o gvdd ? memc_mdq[23] ad10 i/o gvdd ? memc_mdq[24] ae9 i/o gvdd ? memc_mdq[25] ah6 i/o gvdd ? memc_mdq[26] ah5 i/o gvdd ? memc_mdq[27] ag6 i/o gvdd ? memc_mdq[28] ah4 i/o gvdd ? memc_mdq[29] ae6 i/o gvdd ? memc_mdq[30] ad8 i/o gvdd ? memc_mdq[31] af5 i/o gvdd ? memc_mdm0 ae18 o gvdd ? memc_mdm1 ae20 o gvdd ? memc_mdm2 ae10 o gvdd ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 75 package and pin listings memc_mdm3 af6 o gvdd ? memc_mdqs[0] af17 i/o gvdd ? memc_mdqs[1] ag21 i/o gvdd ? memc_mdqs[2] ag9 i/o gvdd ? memc_mdqs[3] af7 i/o gvdd ? memc_mba[0] ah16 o gvdd ? memc_mba[1] ah15 o gvdd ? memc_mba[2] ag15 o gvdd ? memc_ma0 ad15 o gvdd ? memc_ma1 ae15 o gvdd ? memc_ma2 ah14 o gvdd ? memc_ma3 ag14 o gvdd ? memc_ma4 af14 o gvdd ? memc_ma5 ae14 o gvdd ? memc_ma6 ah13 o gvdd ? memc_ma7 ah12 o gvdd ? memc_ma8 af13 o gvdd ? memc_ma9 ad13 o gvdd ? memc_ma10 ag12 o gvdd ? memc_ma11 ah11 o gvdd ? memc_ma12 ah10 o gvdd ? memc_ma13 ae12 o gvdd ? memc_ma14 af11 o gvdd ? memc_mwe ae5 o gvdd ? memc_mras ad7 o gvdd ? memc_mcas ag4 o gvdd ? memc_mcs [0] ah3 o gvdd ? memc_mcs [1] ad5 o gvdd ? memc_mcke ae4 o gvdd 3 memc_mck[0] af4 o gvdd ? memc_mck [0] af3 o gvdd ? memc_mck[1] af1 o gvdd ? memc_mck [1] ae1 o gvdd ? memc_modt[0] ae3 o gvdd ? memc_modt[1] ad4 o gvdd ? memc_mvref ad12 i gvdd ? table 66. mpc8314e tepbga ii pinout listing (continued) signal package pin number pin type power supply note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 76 freescale semiconductor package and pin listings local bus controller interface lad0 ab28 i/o nvdd3 _off 10 lad1 ab27 i/o nvdd3 _off 10 lad2 ac28 i/o nvdd3 _off 10 lad3 aa24 i/o nvdd3 _off 10 lad4 ac27 i/o nvdd3 _off 10 lad5 ad28 i/o nvdd3 _off 10 lad6 ab25 i/o nvdd3 _off 10 lad7 ac26 i/o nvdd3 _off 10 lad8 ad27 i/o nvdd3 _off 10 lad9 ab24 i/o nvdd3 _off 10 lad10 ae28 i/o nvdd3 _off 10 lad11 ae27 i/o nvdd3 _off 10 lad12 ae26 i/o nvdd3 _off 10 lad13 af28 i/o nvdd3 _off 10 lad14 ac24 i/o nvdd3 _off 10 lad15 ad25 i/o nvdd3 _off 10 la16 v24 o nvdd3 _off 10 la17 v25 o nvdd3 _off 10 la18 w26 o nvdd3 _off 10 la19 w28 o nvdd3 _off 10 la20 u24 o nvdd3 _off 10 la21 w24 o nvdd3 _off 10 la22 y28 o nvdd3 _off 10 la23 ah23 o nvdd3 _off 10 la24 ah24 o nvdd3 _off 10 la25 ag23 o nvdd3 _off 10 lcs [0] ad22 o nvdd3 _off 11 lcs [1] af25 o nvdd3 _off 11 lcs [2] ag24 o nvdd3 _off 11 lcs [3] af24 o nvdd3 _off 11 lwe [0] /lfwe /lbs ae23 o nvdd3 _off 11 lwe [1] ag26 o nvdd3 _off 11 lbctl ah26 o nvdd3 _off 11 lale af26 o nvdd3 _off 10 lgpl0/lfcle y27 o nvdd3 _off ? table 66. mpc8314e tepbga ii pinout listing (continued) signal package pin number pin type power supply note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 77 package and pin listings lgpl1/lfale aa28 o nvdd3 _off ? lgpl2/lfre /loe y25 o nvdd3 _off 11 lgpl3/lfwp y24 o nvdd3 _off ? lgpl4/lgta /lupwait/lfrb aa26 i/o nvdd3 _off 2 lgpl5 af22 o nvdd3 _off 11 lclk0 ah25 o nvdd3 _off 10 lclk1 ad24 o nvdd3 _off 10 duart uart_sout1/msrcid0 (ddr id)/lsrcid0 c15 o nvdd2 _off ? uart_sin1/msrcid1 (ddr id)/lsrcid1 b16 i/o nvdd2 _off ? uart_cts [1]/msrcid2 (ddr id)/lsrcid2 d16 i/o nvdd2 _off ? uart_rts [1]/msrcid3 (ddr id)/lsrcid3 b17 o nvdd2 _off ? uart_sout2/msrcid4 (ddr id)/lsrcid4 a16 o nvdd2 _off ? uart_sin2/mdval (ddr id)/ldval c16 i/o nvdd2 _off ? uart_cts [2] a17 i nvdd2 _off ? uart_rts [2] a18 o nvdd2 _off ? i 2 c interface iic_sda/ckstop_out n1 i/o nvdd4 _off 2 iic_scl/ckstop_in n2 i/o nvdd4 _off 2 interrupts mcp_out w1 o nvdd1 _off 2 irq [0]/mcp_in y3 i nvdd1 _off ? irq [1] e1 i nvdd1 _on ? irq [2] a7 i nvdd1 _on ? irq [3] aa1 i nvdd1 _off ? irq [4] y5 i nvdd1 _off ? irq [5]/core_sreset_in aa2 i nvdd1 _off ? irq [6] /ckstop_out aa4 i/o nvdd1 _off ? irq [7]/ckstop_in aa5 i nvdd1 _off ? configuration cfg_clkin_div a5 i nvdd1 _on 11 ext_pwr_ctrl d3 o nvdd1 _on 11 pmc_pwr_ok d4 i ? 11 table 66. mpc8314e tepbga ii pinout listing (continued) signal package pin number pin type power supply note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 78 freescale semiconductor package and pin listings jtag tck e5 i nvdd1 _on ? tdi b4 i nvdd1 _on 4 tdo c4 o nvdd1 _on 3 tms c3 i nvdd1 _on 4 trst c2 i nvdd1 _on 4 tdm gpio_18/tdm_rck ab1 i/o nvdd1 _off ? gpio_20/tdm_rd ac1 i/o nvdd1 _off ? gpio_19/tdm_rfs ab3 i/o nvdd1 _off ? gpio_21/tdm_tck ab5 i/o nvdd1 _off ? gpio_23/tdm_td ac3 i/o nvdd1 _off ? gpio_22/tdm_tfs ac2 i/o nvdd1 _off ? test test_mode d6 i nvdd1 _on 6 debug quiesce b5 o nvdd1 _on ? system control hreset b6 i/o nvdd1 _on 1 poreset a6 i nvdd1 _on ? clocks sys_xtal_in l27 i nvdd2 _on ? sys_xtal_out j28 o nvdd2 _on ? sys_clk_in k28 i nvdd2 _on ? usb_xtal_in a15 i nvdd2 _off ? usb_xtal_out b14 o nvdd2 _off ? usb_clk_in b15 i nvdd2 _off ? pci_sync_out j27 o nvdd2 _on 3 rtc_clk k26 i nvdd2 _on ? pci_sync_in k27 i nvdd2 _on ? misc avdd1 ac15 i ? ? avdd2 m23 i ? ? therm0 l25 i nvdd2 _on 7 dma_dack0 /gpio_13 ac4 i/o nvdd1 _off ? table 66. mpc8314e tepbga ii pinout listing (continued) signal package pin number pin type power supply note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 79 package and pin listings dma_dreq0 /gpio_12 ad1 i/o nvdd1 _off ? dma_done0/gpio_14 ad2 i/o nvdd1 _off ? nc, no connect a2 ? ? ? nc, no connect m25 ? ? ? nc, no connect p26 ? ? ? nc, no connect n25 ? ? ? nc, no connect u26 ? ? ? nc, no connect t25 ? ? ? nc, no connect r26 ? ? ? nc, no connect u25 ? ? ? pci pci_inta b18 o nvdd2 _off ? pci_reset_out a20 o nvdd2 _off ? pci_ad[0] j25 i/o nvdd2 _off ? pci_ad[1] j24 i/o nvdd2 _off ? pci_ad[2] k24 i/o nvdd2 _off ? pci_ad[3] h27 i/o nvdd2 _off ? pci_ad[4] h28 i/o nvdd2 _off ? pci_ad[5] h26 i/o nvdd2 _off ? pci_ad[6] g27 i/o nvdd2 _off ? pci_ad[7] g28 i/o nvdd2 _off ? pci_ad[8] f26 i/o nvdd2 _off ? pci_ad[9] f28 i/o nvdd2 _off ? pci_ad[10] g25 i/o nvdd2 _off ? pci_ad[11] f27 i/o nvdd2 _off ? pci_ad[12] e27 i/o nvdd2 _off ? pci_ad[13] e28 i/o nvdd2 _off ? pci_ad[14] d28 i/o nvdd2 _off ? pci_ad[15] d27 i/o nvdd2 _off ? pci_ad[16] b25 i/o nvdd2 _off ? pci_ad[17] d24 i/o nvdd2 _off ? pci_ad[18] b26 i/o nvdd2 _off ? pci_ad[19] c24 i/o nvdd2 _off ? pci_ad[20] a26 i/o nvdd2 _off ? pci_ad[21] e20 i/o nvdd2 _off ? pci_ad[22] a23 i/o nvdd2 _off ? table 66. mpc8314e tepbga ii pinout listing (continued) signal package pin number pin type power supply note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 80 freescale semiconductor package and pin listings pci_ad[23] c22 i/o nvdd2 _off ? pci_ad[24] e19 i/o nvdd2 _off ? pci_ad[25] a22 i/o nvdd2 _off ? pci_ad[26] c20 i/o nvdd2 _off ? pci_ad[27] b21 i/o nvdd2 _off ? pci_ad[28] d19 i/o nvdd2 _off ? pci_ad[29] a19 i/o nvdd2 _off ? pci_ad[30] a21 i/o nvdd2 _off ? pci_ad[31] b19 i/o nvdd2 _off ? pci_c/be [0] h24 i/o nvdd2 _off ? pci_c/be [1] c27 i/o nvdd2 _off ? pci_c/be [2] a25 i/o nvdd2 _off ? pci_c/be [3] e21 i/o nvdd2 _off ? pci_par g24 i/o nvdd2 _off ? pci_frame c28 i/o nvdd2 _off 5 pci_trdy a24 i/o nvdd2 _off 5 pci_irdy d25 i/o nvdd2 _off 5 pci_stop d23 i/o nvdd2 _off 5 pci_devsel e22 i/o nvdd2 _off 5 pci_idsel d26 i nvdd2 _off ? pci_serr c25 i/o nvdd2 _off 5 pci_perr d21 i/o nvdd2 _off 5 pci_req0 e18 i/o nvdd2 _off ? pci_req1 /cpci_hs_es c18 i nvdd2 _off ? pci_req2 e17 i nvdd2 _off ? pci_gnt0 b20 i/o nvdd2 _off ? pci_gnt1 /cpci_hs_led d17 o nvdd2 _off ? pci_gnt2 /cpci_hs_enum e15 o nvdd2 _off ? m66en l24 i nvdd2 _off ? pci_clk0 e23 o nvdd2 _off ? pci_clk1 f24 o nvdd2 _off ? pci_clk2 e25 o nvdd2 _off ? pci_pme b23 i/o nvdd2 _off 2 etsec1/_usbulpi gpio_24/tsec1_col/u sbdr_txdrxd0 j1 i/o lvdd1 _off ? gpio_25/tsec1_crs/usbdr_txdrxd1 h1 i/o lvdd1 _off ? table 66. mpc8314e tepbga ii pinout listing (continued) signal package pin number pin type power supply note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 81 package and pin listings tsec1_gtx_clk/usbdr_txdrxd2 k5 i/o lvdd1 _off 3 tsec1_rx_clk/usbdr_txdrxd3 j4 i/o lvdd1 _off ? tsce1_rx_dv/usbdr_txdrxd4 j2 i/o lvdd1 _off ? tsec1_rxd[3]/usbdr_txdrxd5 g1 i/o lvdd1 _off ? tsec1_rxd[2]/usbdr_txdrxd6 h3 i/o lvdd1 _off ? tsec1_rxd[1]/usbdr_txdrxd7/tsec _tmr_clk j5 i/o lvdd1 _off ? tsec1_rxd[0]/usbdr_nxt/tsec_tmr _trig1 h2 i lvdd1 _off ? tsec1_rx_er/usbdr_dir/tsec_tmr_ trig2 h5 i lvdd1 _off ? tsec1_tx_clk/usbdr_clk g2 i lvdd1 _off ? gpio_28/tsec1_txd[3]/tsec_tmr_gc lk f3 i/o lvdd1 _off ? gpio_29/tsec1_txd[2]/tsec_tmr_pp1 f2 i/o lvdd1 _off ? gpio_30/tsec1_txd[1]/tsec_tmr_pp2 f1 i/o lvdd1 _off ? tsec1_txd[0]/usbdr_stp/ tsec_tmr_pp3 g4 o lvdd1 _off 11 gpio_31/tsec1_tx_en/tsec_tmr_al arm1 f4 i/o lvdd1 _off ? tsec1_tx_er/tsec_tmr_alarm2 g5 o lvdd1 _off ? tsec_gtx_clk125 d1 i nvdd1 _on ? tsec_mdc/lb_por_cfg_boot_ecc e3 i/o nvdd1 _on 9 tsec_mdio e2 i/o nvdd1 _on etsec2 gpio_26/tsec2_col a8 i/o lvdd2 _on ? gpio_27/tsec2_crs e9 i/o lvdd2 _on ? tsec2_gtx_clk b10 o lvdd2 _on ? tsec2_rx_clk b8 i lvdd2 _on ? tsce2_rx_dv c9 i lvdd2 _on ? tsec2_rxd[3] c10 i lvdd2 _on ? tsec2_rxd[2] d10 i lvdd2 _on ? tsec2_rxd[1] a9 i lvdd2 _on ? tsec2_rxd[0] b9 i lvdd2 _on ? tsec2_rx_er a10 i lvdd2 _on ? tsec2_tx_clk d8 i lvdd2 _on ? tsec2_txd[3]/cfg_reset_source[0] d11 i/o lvdd2 _on ? tsec2_txd[2]/cfg_reset_source[1] c7 i/o lvdd2 _on ? table 66. mpc8314e tepbga ii pinout listing (continued) signal package pin number pin type power supply note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 82 freescale semiconductor package and pin listings tsec2_txd[1]/cfg_reset_source[2] e8 i/o lvdd2 _on ? tsec2_txd[0]/cfg_reset_source[3] b7 i/o lvdd2 _on ? tsec2_tx_en d12 o lvdd2 _on ? tsec2_tx_er b11 o lvdd2 _on ? sgmii / pci express phy txa p4 o xpadvdd ? txa n4 o xpadvdd ? rxa r1 i xcorevdd ? rxa p1 i xcorevdd ? txb u4 o xpadvdd ? txb v4 o xpadvdd ? rxb u1 i xcorevdd ? rxb v1 i xcorevdd ? sd_imp_cal_rx n3 i xcorevdd ? sd_ref_clk r4 i xcorevdd ? sd_ref_clk r5 i xcorevdd ? sd_pll_tpd t2 o ? ? sd_imp_cal_tx v5 i xpadvdd ? sdavdd t3 i ? ? sd_pll_tpa_ana t4 o ? ? sdavss t5 i ? ? usb phy usb_dp a11 i/o usb_vdda ? usb_dm a12 i/o usb_vdda ? usb_vbus c12 i ? ? usb_tpa a14 o ? ? usb_rbias d14 i ? 8 usb_pll_pwr3 a13 i ? ? usb_pll_gnd0 & usb_pll_gnd1 d13 i ? ? usb_pll_pwr1 b13 i ? ? usb_vssa_bias e14 i ? ? usb_vdda_bias c14 i ? ? usb_vssa e13 i ? ? usb_vdda e12 i ? ? gpio gpio_0/dma_dreq1 /gtm1_tout1 c5 i/o nvdd1 _on ? table 66. mpc8314e tepbga ii pinout listing (continued) signal package pin number pin type power supply note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 83 package and pin listings gpio_1/dma_dack1 /gtm1_tin2/gtm2_ tin1 a4 i/o nvdd1 _on ? gpio_2/dma_done1/gtm1_tgate2 /gt m2_tgate1 k3 i/o nvdd4 _off ? gpio_3/gtm1_tin3/gtm2_tin4 k1 i/o nvdd4 _off ? gpio_4/gtm1_tgate3 /gtm2_tgate4 k2 i/o nvdd4 _off ? gpio_5/gtm1_tout3 /gtm2_tout1 l5 i/o nvdd4 _off ? gpio_6/gtm1_tin4/gtm2_tin3 l3 i/o nvdd4 _off ? gpio_7/gtm1_tgate4 /gtm2_tgate3 l1 i/o nvdd4 _off ? gpio_8/usbdr_drive_vbus/gtm1_ti n1/gtm2_tin2 m1 i/o nvdd4 _off ? gpio_9/usbdr_pwrfault/gtm1_tgat e1 /gtm2_tgate2 m2 i/o nvdd4 _off ? gpio_10/usbdr_pctl0/gtm1_tout2 / gtm2_tout1 m5 i/o nvdd4 _off ? gpio_11/usbdr_pctl1/gtm1_tout4 / gtm2_tout3 m4 i/o nvdd4 _off ? spi spimosi/gpio_15 w3 i/o nvdd1 _off ? spimiso/gpio_16 w4 i/o nvdd1 _off ? spiclk y1 i/o nvdd1 _off ? spisel/gpio_17 w2 i/o nvdd1 _off ? power and ground supplies gvdd y11, y12, y14, y15, y17, ac8, ac11, ac14, ac17, ad6, ad9, ad17, ae8, ae13, ae19, af10, af15, af21, ag2, ag3, ag8, ag13, ag19, ah2 i?? lvdd1 _off h6, j3, l6, l9, m9 i ? ? lvdd2 _on c11, d9, e10, f11, j12 i ? ? nvdd1 _off u9, v9, w10, y4, y6, aa3, ab4 i?? nvdd1 _on b1, b2, c1, d5, e7, f5, f9, j11, k10 i ? ? nvdd2 _off b22, b27, c19, e16, f15, f18, f21, f25, h25, j17, j18, j23, l20, m20 i?? nvdd2 _on l26, n19 i ? ? nvdd3 _off u20, v20, v23, v26, w19, y18, y26, aa23, aa25, ac20, ac25, ad23, ae25, ag25, ag27, t27, u27 i?? nvdd4 _off k4, l2, m6, n10 i ? ? table 66. mpc8314e tepbga ii pinout listing (continued) signal package pin number pin type power supply note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 84 freescale semiconductor package and pin listings vdd j15, k15, k16, k17, k18, k19, l10, l19, m10, t10, u10, u19, v10, v19, w11, w12, w13, w14, w15, w16, w17, w18, p23, r23, t19, m26, n26, p28, r28, u23, n27 i?? vddc j14, k11, k12, k13, k14, m19 i?? vss a3, a27, b3, b12, b24, b28, c6, c8, c13, c17, c21, c23, c26, d2, d7, d15, d18, d20, d22, e4, e6, e11, e24, e26, f8, f12, f14, f17, f20, g3, g26, h4, h23, j6, j26, k25, l4, l11, l12, l13, l14, l15, l16, l17, l18, l23, l28, m3, m11, m12, m13, m14, m15, m16, m17, m18, n5, n11, n12, n13, n14, n15, n16, n17, n18, p6, p11, p12, p13, p14, p15, p16, p17, p18, r6, r11, r12, r13, r14, r15, r16, r17, r18, t11, t12, t13, t14, t15, t1 6, t17, t18, u5, u6, u11, u12, u13, u14, u15, u16, u17, u18, v6, v11, v12, v13, v14, v15, v16, v17, v18, w5, w25, w27, y2, y23, aa6, aa27, ab2, ab26, ac5, ac9, ac12, ac18, ac21, ad3, ad14, ad16, ad20, ad26, ae2, ae7, ae11, ae16, ae22 , ae24, af2, af9, af12, af18, af20, af23, af27, ag1, ag5, ag11, ag16, ag22, ag28, ah27, u28,n28, m28, t28, v2 7, m27, v28, t26, p24, r19, r20, r24, m24, n24, p19, p20, p25, p27, r25, r27, t24 i?? xcorevdd p2, p10, r2, t1 i ? ? xcorevss r3, r10, u2, v2 i ? ? xpadvdd p3, r9, u3 i ? ? xpadvss p5, p9, v3 i ? ? note: 1. this pin is an open drain signal. a weak pull-up resistor (1 k ? ) should be placed on this pin to nvdd. 2. this pin is an open drain signal. a weak pull-up resistor (2?10 k ? ) should be placed on this pin to nvdd. 3. this output is actively driven during reset rather than being three-stated during reset. 4. these jtag pins have weak internal pull-up p-fets that are always enabled. 5. this pin should have a weak pull up if the chip is in pci host mode. follow pci specifications recommendation. 6. this pin must always be tied to vss. 7. thermal sensitive resistor. 8. this pin should be connecte d to usb_vssa_bias through 10k precision resistor. 9. the lb_por_cfg_boot_ecc functionality for this pin is on ly available in mpc8314e revision 1.1 and later. the lb_por_cfg_boot_ecc is sampled only during the poreset negation. this pin with an internal pull down resistor enables the ecc by default. to disable the ecc an external st rong pull up resistor or a tristate buffer is needed. 10.this pin has a weak internal pull-down. 11.this pin has a weak internal pull-up. table 66. mpc8314e tepbga ii pinout listing (continued) signal package pin number pin type power supply note
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 85 clocking 23 clocking this figure shows the inte rnal distribution of cloc ks within the mpc8314e 1 multiplication factor m = 1, 1.5, 2, 2.5, and 3. value is decided by rcwlr[corepll]. 2 multiplication factor l = 2, 3, 4 and 5. value is decided by rcwlr[spmf]. figure 60. mpc8314e clock subsystem system lbc lclk[0:1] e300c3 core csb_clk to rest csb_clk local bus pci_clk_out[0:2] pci_sync_out pci_clk/ clock unit of the device lbc_clk _div pci clock pci_sync_in memory device /n to local bus clock divider (? 2) 3 memc_mck memc_mck ddr ddr_clk ddr memory device pll to ddr memory controller clock cfg_clkin /2 divider divider 1 0 usb mac usb phy pll etsec protocol converter gtx_clk125 125-mhz source sys_xtal_in sys_xtal_out mux crystal sys_clk_in usb_xtal_in usb_xtal_out crystal usb_clk_in /1,/2 rtc_clk (32 khz) rtc sys ref core pll core_clk x l 2 x m 1 tdm /n pci express protocol converter 125/100 mhz pll pcvtr mux serdes phy + - sd_ref_clk_b sd_ref_clk mpc8314e
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 86 freescale semiconductor clocking the primary clock source can be one of two inputs, sys_clk_in or pci_clk, depending on whether the device is configured in pci hos t or pci agent mode. when the device is configured as a pci host device, sys_clk_in is its pr imary input clock. sys_clk_in feeds the pci cl ock divider ( ? 2) and the multiplexors for pci_sync_out and pci_clk_out. the cfg_sys_clkin_div configuration input selects whether sys_clk_in or sys_clk_in /2 is driven out on the pci_sync_out signal. pci_sync_out is connected externally to pci_sy nc_in to allow the internal clock subsystem to synchronize to the system pci clocks. pci_sync_out must be connected properly to pci_sync_in, with equal delay to all pci agent devices in the system, to allow the device to function. when the device is configured as a pci agent device, pci_clk is the primary input cloc k. when the device is configured as a pci agent device the sys_clk_ in signal should be tied to gnd. as shown in figure 60 , the primary clock input (frequency) is multiplied up by the system phase-locked loop (pll) and the clock unit to create the cohere nt system bus clock ( csb_clk ), the internal clock for the ddr controller ( ddr_clk ), and the internal clock for the local bus interface unit ( lbiu_clk ). the csb_clk frequency is derived from a co mplex set of factors that can be simplified into the following equation: csb_clk = {pci_sync_in (1 + ~ cfg_sys_clkin_div )} spmf in pci host mode, pci_sync_in (1 + ~ cfg_sys_clkin_div ) is the sys_clk_in frequency. the csb_clk serves as the clock input to the e300 core. a second pll inside the e300 core multiplies up the csb_clk frequency to create the internal clock for the e300 core ( core_clk ). the system and core pll multipliers are selected by the spmf and corepll fi elds in the reset confi guration word low (rcwl) which is loaded at power-on reset or by one of the hard-coded reset options. see chapter 4, ?reset, clocking, and initia lization,? in the mpc8315e powerquicc ii pro integr ated host processor family reference manual for more information on the clock subsystem. the internal ddr_clk frequency is determined by the following equation: ddr_clk = csb_clk (1 + rcwl[ddrcm]) note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the ddr clock divider ( ? 2) to create the differential ddr me mory bus clock outputs (mck and mck ). however, the data rate is the same frequency as ddr_clk . the internal lbiu_clk frequency is determined by the following equation: lbiu_clk = csb_clk (1 + rcwl[lbcm]) note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the lbiu clock divider to create the external local bus cloc k outputs (lclk[0:1]). the lbiu cloc k divider ratio is controlled by lcrr[clkdiv]. in addition, some of the internal uni ts may be required to be shut off or operate at lower frequency than the csb_clk frequency. those units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. table 67 specifies which units have a configurable clock frequency.
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 87 clocking this table provides the operating frequencies for the tepbga ii under recommended operating conditions (see table 2 ). 23.1 system pll configuration the system pll is controlled by the rcwl[spmf] parameter. table 69 shows the multiplication factor encodings for the system pll. note if rcwl[ddrcm] and rcwl[lbcm] ar e both cleared, the system pll vco frequency = (csb frequency) ? (system pll vco divider). if either rcwl[ddrcm] or rcwl[lbc m] are set, the system pll vco frequency = 2 ? (csb frequency) ? (system pll vco divider). the vco divider needs to be set pr operly so that the system pll vco frequency is in the range of 450?750 mhz. table 67. configurable clock units unit default frequency options etsec1 csb_clk off, csb_clk, csb_clk/2, csb_clk/3 etsec2 csb_clk off, csb_clk, csb_clk/2, csb_clk/3 security core, i2c, sap, tpr csb_clk off, csb_clk, csb_clk/2, csb_clk/3 usb dr csb_clk off, csb_clk, csb_clk/2, csb_clk/3 pci and dma complex csb_clk off, csb_clk pci express csb_clk off, csb_clk serial ata csb_clk off, csb_clk, csb_clk/2, csb_clk/3 table 68. operating frequencies for tepbga ii characteristic 1 max operating frequency unit e300 core frequency ( core_clk ) 400 mhz coherent system bus frequency ( csb_clk ) 133 mhz ddr1/2 memory bus frequency (mck) 2 133 mhz local bus frequency (lclk n ) 3 66 mhz pci input frequency (sys_clk_ in or pci_clk) 24-66 mhz note: 1. the sys_clk_in frequency, rcwl[spmf], and rcwl[corepll] setti ngs must be chosen su ch that the resulting csb_clk , mck, lclk[0:1], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. 2. the ddr data rate is 2x the ddr memory bus frequency. 3. the local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on lcrr[clkdiv]) which is in turn 1x or 2x the csb_clk frequency (depending on rcwl[lbcm]).
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 88 freescale semiconductor clocking as described in section 23, ?clocking ,? the lbcm, ddrcm, and spmf parameters in the reset configuration word low and the cfg_sys_clkin_div configuration input signal select the ratio between the primary clock input (sys _clk_in or pci_clk) a nd the internal coherent system bus clock ( csb_clk ). table 70 and table 71 shows the expected frequency values for the csb frequency for select csb_clk to sys_clk_in/pci_sync_in ratios. table 69. system pll multiplication factors rcwl[spmf] system pll multiplication factor 0000 reserved 0001 reserved 0010 ? 2 0011 ? 3 0100 ? 4 0101 ? 5 0110?1111 reserved table 70. csb frequency options for host mode cfg_sys_clkin_div at reset 1 1 cfg_sys_clkin_div select the ratio between sys_clk_in and pci_sync_out. spmf csb_clk : input clock ratio 2 2 sys_clk_in is the input clock in host mode; pci_clk is the input clock in agent mode. input clock frequency (mhz) 2 24 33.33 66.67 high/low 3 3 in the host mode it does not matter if the value is high or low. 0010 2:1 133 high/low 0011 3:1 100 ? high/low 0100 4:1 96 133 ? high/low 0101 5:1 120 ? ? table 71. csb frequency options for agent mode cfg_sys_clkin_div at reset 1 1 cfg_sys_clkin_div doubles csb_clk if set low. spmf csb_clk : input clock ratio 2 2 sys_clk_in is the input clock in host mode; pci_clk is the input clock in agent mode. input clock frequency (mhz) 2 25 33.33 66.67 high 0010 2: 1 133 high 0011 3: 1 100 ? high 0100 4: 1 133 ? high 0101 5: 1 120 ? ?
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 89 clocking 23.2 core pll configuration rcwl[corepll] selects the ratio between th e internal coherent system bus clock ( csb_clk ) and the e300 core clock ( core_clk ). table 72 shows the encodings for rcwl[cor epll]. corepll values that are not listed in table 72 should be considered as reserved. note core vco frequency = core frequency ?? vco divider ? vco divider has to be set properly so th at the core vco frequency is in the range of 400?800 mhz. 23.3 suggested pll configurations to simplify the pll configurations , the mpc8314e might be separated into two clock domains. the first domain contain the csb pll and the core pll. the core pll is connected serially to the csb pll, and has the csb_clk as its input clock. the clock domai ns are independent, and each of their plls are configured separately. both of the domains has one co mmon input clock. table 73 shows suggested pll configurations for 33, 25, and 66 mhz input clocks. table 72. e300 core pll configuration rcwl[corepll] core_clk : csb_clk ratio vco divider 1 1 core vco frequency = core frequency ? vco divider. 0?1 2?5 6 nn 0000 0 pll bypassed (pll off, csb_clk clocks core directly) pll bypassed (pll off, csb_clk clocks core directly) 11 nnnn nn/a n/a 00 0001 01:1 2 01 0001 01:1 4 00 0001 1 1.5:1 2 01 0001 1 1.5:1 4 00 0010 02:1 2 01 0010 02:1 4 00 0010 1 2.5:1 2 01 0010 1 2.5:1 4 00 0011 03:1 2 01 0011 03 : 1 4 table 73. suggested pll configurations conf. no. spmf core\pll input clock frequency (mhz) csb frequency (mhz) core frequency (mhz) 1 0100 0000100 33.33 133.33 266.66 3 0010 0000100 66.67 133.33 266.66 4 0100 0000101 33.33 133.33 333.33 5 0101 0000101 25 125 312.5
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 90 freescale semiconductor thermal 24 thermal this section describes the thermal specifications of the mpc8314e. 24.1 thermal characteristics this table provides the package thermal characteristics for the 620 29 ? 29 mm tepbga ii. 6 0010 0000101 66.67 133.33 333.33 7 0101 0000110 25 125 375 8 0100 0000110 33.33 133.33 400 9 0010 0000110 66.67 133.33 400 table 74. package thermal characteristics for tepbga ii characteristic board type symbol value unit note junction to ambient natural convection single layer board (1s) r ? ja 23 c/w 1, 2 junction to ambient natural convection four layer board (2s2p) r ? ja 16 c/w 1, 2, 3 junction to ambient (@200 ft/min) single layer board (1s) r ? jma 18 c/w 1, 3 junction to ambient (@200 ft/min) four layer board (2s2p) r ? jma 13 c/w 1, 3 junction to board ? r ? jb 8c/w4 junction to case ? r ? jc 6c/w5 junction to package top natural convection ? jt 6c/w6 note: 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, po wer dissipation of other components on the board, and board thermal resistance. 2. per jedec jesd51-2 with the single layer board horizontal. board meets jesd51-9 specification. 3. per jedec jesd51-6 with the board horizontal. 4. thermal resistance between the die and the printed circuit bo ard per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surf ace as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the te mperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are no t available, the thermal characterization parameter is written as psi-jt. table 73. suggested pll configurations conf. no. spmf core\pll input clock frequency (mhz) csb frequency (mhz) core frequency (mhz)
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 91 thermal 24.2 thermal management information for the following sections, p d = (vdd ? i dd ) + p i/o where p i/o is the power dissipati on of the i/o drivers. 24.2.1 estimation of junction temperature with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r ? ja ? p d ) where: t j = junction temperature ( ? c) t a = ambient temperature for the package ( ? c) r ? ja = junction to ambient thermal resistance ( ? c/w) p d = power dissipation in the package (w) the junction to ambient thermal resistance is an i ndustry standard value that provides a quick and easy estimation of thermal performance. as a general statement, the value obtained on a single layer board is appropriate for a tightly packed printed circuit boar d. the value obtained on the board with the internal planes is usually appropriate if th e board has low power diss ipation and the components are well separated. test cases have demonstrated that errors of a factor of two (in the quantity t j - t a ) are possible. 24.2.2 estimation of junction temperature with junction-to-board thermal resistance the thermal performance of a device cannot be adequa tely predicted from the j unction to ambient thermal resistance. the thermal performan ce of any component is strongly de pendent on the power dissipation of surrounding components. in addition, the ambient temperature varies wi dely within the application. for many natural convection and especially closed box applications, the boa rd temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determ ine the temperature of the device. at a known board temperature, th e junction temperature is estima ted using the following equation: t j = t b + (r ? jb ? p d ) where: t j = junction temperature ( ? c) t b = board temperature at the package perimeter ( ? c) r ? jb = junction to board thermal resistance ( ? c/w) per jesd51-8 p d = power dissipation in the package (w) when the heat loss from the package case to the ai r can be ignored, acceptable predictions of junction temperature can be made. the appli cation board should be similar to the thermal test condition: the component is soldered to a board with internal planes.
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 92 freescale semiconductor thermal 24.2.3 experimental determinat ion of junction temperature to determine the junction temperatur e of the device in the application after prototypes are available, the thermal characterization parameter ( ? jt ) can be used to determine th e junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( ? jt ? p d ) where: t j = junction temperature ( ? c) t t = thermocouple temperature on top of package ( ? c) ? jt = junction to ambient thermal resistance ( ? c/w) p d = power dissipation in the package (w) the thermal characterization parame ter is measured per jesd51-2 spec ification using a 40 gauge type t thermocouple epoxied to the top center of the pack age case. the thermocouple should be positioned so that the thermocouple junction rests on the packag e. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from th e junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 24.2.4 heat sinks and juncti on-to-case thermal resistance in some application envir onments, a heat sink is required to provide the necessary thermal management of the device. when a heat sink is used, the thermal resi stance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: r ? ja = r ? jc + r ? ca where: r ? ja = junction to ambient thermal resistance ( ? c/w) r ? jc = junction to case th ermal resistance ( ? c/w) r ? ca = case to ambient thermal resistance ( ? c/w) r ? jc is device related and cannot be influenced by the user. the user controls the thermal environment to change the case to ambient thermal resistance, r ? ca . for instance, the user can ch ange the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on th e printed circuit board surrounding the device. to illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few commercially available heat sinks. the heat sink choice is determined by the application environment (temperature, air flow, ad jacent component power dissipation) and the physical space available. because there is not a standard appl ication environment, a standard heat sink is not required.
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 93 thermal accurate thermal design requires thermal modeling of the application environm ent using computational fluid dynamics software which can model both the conduction cooling a nd the convection cooling of the air moving through the application. si mplified thermal models of the pa ckages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in th e thermal resistance table. more detailed thermal models can be made available on request. heat sink vendors include the following list: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com alpha novatech 408-749-7601 473 sapena ct. #12 santa clara, ca 95054 internet: www.alphanovatech.com international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com table 75. heat sinks and junction-to-case thermal resistance of mpc8314e tepbga ii heat sink assuming thermal grease air flow 29 ? 29 mm tebga ii junction-to-ambient thermal resistance aavid 30 x 30 x 9.4 mm pin fin natural convection 14.4 aavid 30 x 30 x 9.4 mm pin fin 0.5 m/s 11.4 aavid 30 x 30 x 9.4 mm pin fin 1 m/s 10.1 aavid 30 x 30 x 9.4 mm pin fin 2 m/s 8.9 aavid 35 x 31 x 23 mm pin fin natural convection 12.3 aavid 35 x 31 x 23 mm pin fin 0.5 m/s 9.3 aavid 35 x 31 x 23 mm pin fin 1 m/s 8.5 aavid 35 x 31 x 23 mm pin fin 2 m/s 7.9 aavid 43 x 41 x 16.5 mm pin fin natural convection 12.5 aavid 43 x 41 x 16.5 mm pin fin 0.5 m/s 9.7 aavid 43 x 41 x 16.5 mm pin fin 1 m/s 8.5 aavid 43 x 41 x 16.5 mm pin fin 2 m/s 7.7 wakefield, 53 x 53 x 25 mm pin fin natural convection 10.9 wakefield, 53 x 53 x 25 mm pin fin 0.5 m/s 8.5 wakefield, 53 x 53 x 25 mm pin fin 1 m/s 7.5 wakefield, 53 x 53 x 25 mm pin fin 2 m/s 7.1
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 94 freescale semiconductor thermal millennium electronics (mei) 408-436-8770 loroco sites 671 east brokaw road san jose, ca 95112 internet: www.mei-thermal.com tyco electronics 800-522-6752 chip coolers? p.o. box 3668 harrisburg, pa 17105 internet: www.tycoelectronics.com wakefield engineering 603-635-2800 33 bridge st. pelham, nh 03076 internet: www.wakefield.com interface material vendors include the following: chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01801 internet: www.chomerics.com dow-corning corporation 800-248-2481 corporate center po box 994 midland, mi 48686-0994 internet: www.dowcorning.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com the bergquist company 800-347-4572 18930 west 78th st. chanhassen, mn 55317 internet: www.bergquistcompany.com 24.3 heat sink attachment when attaching heat sinks to these devices, an inte rface material is required. the best method is to use thermal grease and a spring clip. the spring clip shoul d connect to the printed circuit board, either to the board itself, to hooks soldered to th e board, or to a plastic stiffener. avoid attachment fo rces which would lift the edge of the package or peel the package from the board. such peeling forc es reduce the solder joint lifetime of the package. recomm ended maximum force on the top of the package is 10 lb force (45 newtons). if an adhesive attachme nt is planned, the adhesive should be intended for attachment to painted or plastic surfaces and its performance ve rified under the application requirements.
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 95 system design information 24.3.1 experimental determination of the junction temperature with a heat sink when heat sink is used, the juncti on temperature is determined from a thermocouple inserted at the interface between the case of the package and the in terface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink temperature and then back calculate the case temperature using a sepa rate measurement of the thermal resistance of the interface. from this case temperat ure, the junction temperature is de termined from the junction to case thermal resistance. t j = t c + (r ? jc x p d ) where t c is the case temperature of the package r ? jc is the junction-to-c ase thermal resistance p d is the power dissipation 25 system design information this section provides elect rical and thermal design r ecommendations for successf ul application of the mpc8314e. 25.1 system clocking the mpc8314e includes two plls. 1. the platform pll (avdd2) generates the pl atform clock from the externally supplied sys_clk_in input. the frequency ratio between the platform and sys_clk_in is selected using the platform pll ratio conf iguration bits as described in section 23.1, ?system pll configuration .? 2. the e300 core pll (avdd1 ) generates the core clock as a sl ave to the platform clock. the frequency ratio between the e300 core clock and the platform cl ock is selected using the e300 pll ratio configuration bits as described in section 23.2, ?core pl l configuration.? 25.2 pll power supply filtering each of the plls listed above is provided with power through indepe ndent power supply pins (avdd1,avdd2 respectively). the av dd level should always be equiva lent to vdd, and preferably these voltages are derived directly from vdd through a low frequency filt er scheme such as the following. there are a number of ways to reliably provide power to the plls, but the recommended solution is to provide independent filter circuits as illustrated in figure 61 , one to each of the av dd pins. by providing independent filters to each pll th e opportunity to cause noise injection from one pll to the other is reduced.
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 96 freescale semiconductor system design information this circuit is intended to filter noise in the p lls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacitor s with minimum effective series inductance (esl). consistent with the recommenda tions of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacito rs of equal value are recommended over a single large value capacitor. each circuit should be placed as close as possible to the specific av dd pin being supplied to minimize noise coupled from nearby circuits. it should be possible to route direct ly from the capacitors to the av dd pin, which is on the periphery of packag e, without the inductance of vias. no te that the rc fi lter results in lower voltage level on avdd. this does not imply that the dc specification can be relaxed. this figure shows the pll pow er supply filter circuit. figure 61. pll power supply filter circuit 25.3 decoupling recommendations due to large address and data buses, and high opera ting frequencies, the device can generate transient power surges and high freque ncy noise in its power suppl y, especially while drivi ng large capacitive loads. this noise must be prevented from reaching ot her components in the mpc8314e system, and the mpc8314e itself requires a clean, tight ly regulated source of power. ther efore, it is recommended that the system designer pl ace at least one decoupling capacitor at each vdd, nvdd, g vdd, and lvdd pins of the device. these decoupling capacitors should receive their power from separate vdd, nvdd, gvdd, lvdd, and gnd power planes in the pcb, utilizing thick and short traces to minimize inductance. capacitors may be place d directly under the device using a standard escape pattern. others may surround the part. these capacitors should have a va lue of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be severa l bulk storage capacitors distributed around the pcb, feeding the vdd, nvdd, gvdd, and lvdd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors shoul d have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connect ed to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). 25.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to nvdd, gvdd, or lvdd as required. unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. vdd av dd (or l2av dd ) 2.2 f 2.2 f gnd low esl surface mount capacitors 10 ??
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 97 system design information power and ground connections must be made to all external vdd, gvdd, lvdd, nvdd , and gnd pins of the device. 25.5 output buffer dc impedance the mpc8314e drivers are characterize d over process, voltage, and temper ature. for all buses, the driver is a push-pull single-ended driv er type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external resistor is connected from the chip pad to nvdd or gnd. then, the value of each resistor is varied until the pad voltage is nvdd/2 (see figure 62 ). the output impedance is the av erage of two components, the resistances of the pul l-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals nvdd/2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. figure 62. driver impedance measurement the value of this resistance and the strength of the driver?s current source can be found by making two measurements. first, the out put voltage is measured while driving l ogic 1 without an exte rnal differential termination resistor. the measured voltage is v 1 = r source ? i source . second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value r term . the measured voltage is v 2 =(1/(1/r 1 +1/r 2 )) ? i source . solving for the output impedance gives r source = r term ? (v 1 /v 2 ? 1). the drive current is then i source =v 1 /r source . nvdd ognd r p r n pad data sw1 sw2
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 98 freescale semiconductor ordering information this table summarizes the signal im pedance targets. the driver impeda nce are targeted at minimum vdd, nominal nvdd, 105? c. 25.6 configuration pin multiplexing the mpc8314e provides the user with power-on configuration options that can be set through the use of external pull-up or pull- down resistors of 4.7 k ? on certain output pins (see cu stomer visible configuration pins). these pins are generally used as output only pins in normal operation. while hreset is asserted however, these pins are treated as inputs. the value presented on these pins while hreset is asserted, is latched when poreset deasserts, at which time the input receiver is disabled and the i/o circuit takes on its normal function. careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of si gnal quality or speed for out put pins thus configured. 25.7 pull-up resistor requirements the mpc8314e requires high resi stance pull-up resistors (10 k ? is recommended) on open drain type pins including i 2 c pins and epic interrupt pins. for more information on required pull up resistors and the connections required for jtag interface, see an3438, mpc8315 design checklist 26 ordering information ordering information for the part s fully covered by this specifi cation document is provided in section 26.1, ?part numbers fully addressed by this document.? 26.1 part numbers fully addressed by this document this table provides the freescal e part numbering nomenclature fo r the mpc8314e. note that the individual part numbers correspond to a maximum processor core frequency. for available frequencies, contact your local freescale sales offi ce. in addition to the processor fre quency, the part numbering scheme table 76. impedance characteristics impedance local bus, ethernet, duart, control, configuration, power management pci signals (not including pci output clocks) pci output clocks (including pci_sync_out) ddr dram symbol unit r n 42 target 25 target 42 target 20 target z 0 ? r p 42 target 25 target 42 target 20 target z 0 ? differential na na na na z diff ? note: nominal supply voltages. see ta b l e 1 , t j = 105 ? c.
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 freescale semiconductor 99 ordering information also includes an application modifi er which may specify sp ecial application conditi ons. each part number also contains a revision code which re fers to the die mask revision number. this table shows the svr setti ngs by device and package type. table 77. part numbering nomenclature mpc 8314 ec vr ag d a product code part identifier encryption acceleration temperature range 3 package 1 e300 core frequency 2 ddr frequency revision level mpc 8314 blank = not included e = included blank = 0 to 105 ? c c = ?40 to 105 ? c vr= pb free tepbga ii ad = 266 mhz af = 333 mhz ag = 400 mhz d = 266 mhz contact local freescale sales office note: 1. see section 22, ?package and pin listings,? for more information on available package types. 2. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specifica tion support all core frequencies. additionally, parts addresse d by electric may support other maximum core frequencies. 3. contact your local freescale field applications engineer (fae). table 78. svr settings device package svr (rev 1.0) svr (rev 1.1) svr (rev 1.2) mpc8314e tepbga ii 0x80b6_0010 0x80b6_0011 0x80b6_0012 mpc8314 tepbga ii 0x80b7_0010 0x80b7_0011 0x80b7_0012 note: 1. pvr = 8085_0020 for all devices and revisions in this table.
mpc8314e powerquicc ii pro processor hardware specifications, rev. 2 100 freescale semiconductor revision history 27 revision history this table summarizes a revision history for this document. table 79. revision history revision date substantive change(s) 2 11/2011 ? in ta b l e 6 6 : ? corrected note 10 to pull down. ? added pull up information. 1 11/2011 ? added notes 4, 5, 6, and 7 in ta bl e 2 . ?in ta b l e 6 : ? decoupled pci_clk and sys_clk_in rise and fall times. ? relaxed maximum rise/fall time of sys_clk_in from 1.2 ns to 4 ns. ? modified note 2. ? updated sys_clk_in/pci _clk frequency from 66 mhz to 66.67 mhz. ? added note 4 to ta b l e 9 . ? added a note stating ?etsec should be interfaced with peripheral operating at same voltage level.? in section 9.1.1, ?mii, rmii, rgmii, and rtbi dc electrical characteristics .? ? added a note in ta bl e 2 6 stating ?the frequency of rx_clk should not exceed the tx_clk by more than 300 ppm." ? added a note in ta b l e 2 9 stating ?the frequency of rx_clk should not exceed the gtx_clk125 by more than 300 ppm ?in ta b l e 4 2 , changed min/max values of t clk_tol from 0.05 to 0.005. ? added t lalehov parameter to ta bl e 4 4 ? replaced 50 with 50 ?? in section 16.5, ?receiver compliance eye diagrams.? ?in ta b l e 6 6 : ? added pull up and pull down information. ? removed note 2 from tsec_mdio. ? removed configuration 2 from ta b l e 7 3 . ? removed preliminary from section 24, ?thermal.? ? removed mdio signal from section 25.7, ?pull-up resistor requirements ? as this signal is not open drain. ? replaced lccr with lcrr throughout. ? replaced sys_clkin wi th sys_clk_in throughout. ? replaced all lbiucm with lbcm. ? replaced all sys_cr_clk_in and sys_ cr_clk_out with sys_xtal_in and sys_xtal_out, respectively. replaced a ll usb_cr_clk_in and usb_cr_clk_out with usb_xtal_in and usb_xt al_out, respectively. ? added rise/fall time spec for tdm clk 0 05/2009 initial public release
document number: mpc8314eec rev. 2 11/2011 information in this document is provid ed solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental da mages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or spec ifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale and the freescale logo are trademarks of freescale semiconductor, inc. reg. u.s. pat. & tm. off. qoriq is a trademark of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? 2011 freescale semiconductor, inc.

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